公开(公告)号：US20140367825A1

公开(公告)日：2014-12-18

申请号：US14274002

申请日：2014-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Rae KIM ,  Byoung-Deog CHOI ,  Hee-Young PARK ,  Sang-Ho ROH ,  Jin-Hyung PARK ,  Kyung-Mun BYUN

IPC: H01L29/06 ,  H01L21/764

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

Abstract: Semiconductor devices including empty spaces and methods of forming the semiconductor devices are provided. The semiconductor devices may include first and second line structures extending in a direction on a substrate, an insulating isolation pattern between the first and second line structures and a conductive structure between the first and second line structures and next to the insulating isolation pattern along the direction. The semiconductor devices may also include an empty space including a first portion between the first line structure and the conductive structure and a second portion between the first line structure and the insulating isolation pattern. The first portion of the empty space may have a height different from a height of the second portion of the empty space.

Abstract translation: 提供包括空白空间的半导体器件和形成半导体器件的方法。 半导体器件可以包括沿着衬底上的方向延伸的第一和第二线结构，在第一和第二线结构之间的绝缘隔离图案以及在第一和第二线结构之间的导电结构，并且沿绝缘隔离图案沿着方向 。 半导体器件还可以包括空白空间，其包括第一线结构和导电结构之间的第一部分和第一线结构与绝缘隔离图案之间的第二部分。 空白空间的第一部分可以具有与空白空间的第二部分的高度不同的高度。

公开(公告)号：US20180012775A1

公开(公告)日：2018-01-11

申请号：US15613822

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Mun BYUN ,  Badro IM ,  Hong-Rae KIM ,  Sin-Hae DO ,  Gyeong-Deok PARK

IPC: H01L21/48 ,  H01L21/764 ,  H01L21/308 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8234 ,  H01L21/67

CPC classification number: H01L21/4885 ,  H01L21/28132 ,  H01L21/28194 ,  H01L21/28556 ,  H01L21/308 ,  H01L21/67138 ,  H01L21/764 ,  H01L21/768 ,  H01L21/823475

Abstract: In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.