公开(公告)号：US20230122691A1

公开(公告)日：2023-04-20

申请号：US17865811

申请日：2022-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyusik KIM ,  Seungjin KIM ,  Seunghyun OH

IPC: H03L7/091 ,  H03L7/099

Abstract: A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.