公开(公告)号：US10573679B2

公开(公告)日：2020-02-25

申请号：US16001461

申请日：2018-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-won Kwon

IPC: H01L27/146 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00

Abstract: A stacked complementary metal oxide semiconductor (CMOS) image sensor includes: a first semiconductor chip in which a plurality of pixels are in an upper area in a two-dimensional array structure and a first wiring layer is in a lower area; and a second semiconductor chip in which a second wiring layer is arranged in an upper area and logic elements are in a lower area, wherein the first semiconductor chip is coupled to the second semiconductor chip through a connection between a first metal pad in a first pad insulating layer in a lowermost portion of the first wiring layer and a second metal pad in a second pad insulating layer in an uppermost portion of the second wiring layer, and wherein a metal-insulator-metal (MIM) capacitor is in at least one of the first pad insulating layer and the second pad insulating layer.

公开(公告)号：US20190123088A1

公开(公告)日：2019-04-25

申请号：US16001461

申请日：2018-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-won Kwon

IPC: H01L27/146 ,  H01L23/522 ,  H01L23/00

Abstract: A stacked complementary metal oxide semiconductor (CMOS) image sensor includes: a first semiconductor chip in which a plurality of pixels are in an upper area in a two-dimensional array structure and a first wiring layer is in a lower area; and a second semiconductor chip in which a second wiring layer is arranged in an upper area and logic elements are in a lower area, wherein the first semiconductor chip is coupled to the second semiconductor chip through a connection between a first metal pad in a first pad insulating layer in a lowermost portion of the first wiring layer and a second metal pad in a second pad insulating layer in an uppermost portion of the second wiring layer, and wherein a metal-insulator-metal (MIM) capacitor is in at least one of the first pad insulating layer and the second pad insulating layer.

公开(公告)号：US09165974B2

公开(公告)日：2015-10-20

申请号：US14486389

申请日：2014-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-kwan Kim ,  Doo-won Kwon ,  Jeong-ki Kim ,  Wook-hwan Kim ,  Byung-jun Park ,  Seung-hun Shin ,  June-taeg Lee ,  Ha-kyu Choi ,  Tae-seok Oh

IPC: H01L31/00 ,  H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14643 ,  H01L24/80 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/1469 ,  H01L2224/05547 ,  H01L2224/08121 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.

Abstract translation: 电子器件可以包括第一半导体层，半导体层上的第一电极层，第一电极层上的粘合绝缘层，粘合绝缘层上的第二电极层，第二半导体层。 第一电极层可以包括第一多个电极，第一电极层可以在粘合绝缘层和第一半导体层之间，并且粘合绝缘层可以包括SiOCN，SiBN和/或BN中的至少一种。 第二电极层可以包括第二多个电极，粘合绝缘层可以在第一和第二电极层之间，并且第二电极层可以在粘合绝缘层和第二半导体层之间。