公开(公告)号：US20240405969A1

公开(公告)日：2024-12-05

申请号：US18807395

申请日：2024-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taechan KIM ,  Hyesun KWAK ,  Jinyeong SEO ,  Yongsoo SONG ,  Dongwon LEE

IPC: H04L9/06 ,  H04L9/00

Abstract: An electronic device for generating a homomorphic ciphertext, includes: at least one processor, memory storing instructions that, when executed by the at least one processor, cause the electronic device to: identify one or more messages; encode each of the one or more messages to generate a first set and a second set each including one or more ciphertexts; output a third set corresponding to a multi-key by applying a public key based on the first set and the second set; and control generation of the first set and the second set and the output of the third set to operate with a complexity of O(n), wherein n is equal to a number of the one or more messages and a number of the one or more ciphertexts.

公开(公告)号：US20250133733A1

公开(公告)日：2025-04-24

申请号：US18886045

申请日：2024-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyesung PARK ,  Jonghyuk PARK ,  Seungji KANG ,  Seongeun KIM ,  Jinwoo BAE ,  Dongwon LEE ,  Juyeon HAN

IPC: H10B12/00

Abstract: A semiconductor device may include a substrate with a memory cell area including a first active area and a peripheral circuit area including a second active area, a capacitor structure including a first electrode connected to the first active area in the memory cell area, a second electrode including a silicon containing layer surrounding the first electrode on the memory cell area and a metal plate layer on the silicon containing layer, an interlayer insulating layer on the peripheral circuit area, and a capping insulating layer covering the capacitor structure on the memory cell area and covering the interlayer insulating layer on the peripheral circuit area. The capacitor structure may include a capacitor dielectric layer between the first and second electrode. The metal plate layer may be on an upper surface of the silicon containing layer and may not be on a side surface of the silicon containing layer.