公开(公告)号：US20250139003A1

公开(公告)日：2025-05-01

申请号：US18783598

申请日：2024-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunju Yi ,  Byungchul Ko

IPC: G06F12/02 ,  G06F12/1045 ,  G06F13/16

Abstract: Provided is an operating method of a storage controller that includes a buffer memory, an address manager, and a direct memory access (DMA) engine and controls a non-volatile memory device. The operating method includes receiving, from an external host device, a read request including a host address, storing, by an address manager in response to the read request, mapping information about the host address and a command identifier corresponding to the read request in a translation table, setting, by the DMA engine, a destination address of read data corresponding to the read request to a virtual address corresponding to the command identifier, and transmitting the read data to the virtual address, and translating, by the address manager based on the translation table, the destination address of the read data from the virtual address to the host address.

公开(公告)号：US12271605B2

公开(公告)日：2025-04-08

申请号：US17944613

申请日：2022-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ranhee Lee ,  Byungchul Ko

IPC: G06F21/79 ,  G06F3/06

Abstract: A storage device and an operation method of a storage device is provided. An operation method of a storage device includes: detecting an abnormal operation of a host memory buffer (HMB) positioned outside a storage device during data processing; and when the abnormal operation is detected, updating, by the storage device, a security policy applied when writing data to or reading data from the HMB.

公开(公告)号：US09792974B2

公开(公告)日：2017-10-17

申请号：US14966039

申请日：2015-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewoong Ha ,  Byungchul Ko ,  Daekyoung Kim ,  Jonghwan Kim

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4093 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G11C7/1045 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2211/4067

Abstract: A memory system including a plurality of dynamic random access memory (DRAM) devices and a DRAM controller is provided. The plurality of DRAM devices includes one or more DRAM groups. Each of the one or more DRAM groups includes at least two DRAM devices. The DRAM controller outputs a clock enable signal, and controls a selection signal used to select a target DRAM device that operates in a normal mode in response to the clock enable signal. At least one target DRAM device is selected from the one or more DRAM groups. One or more stand-by DRAM devices other than the at least one target DRAM device operates in a self-refresh mode.

公开(公告)号：US12299321B2

公开(公告)日：2025-05-13

申请号：US17958593

申请日：2022-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ranhee Lee ,  Byungchul Ko

IPC: G06F3/06

Abstract: Disclosed is an operation method of a storage device, which includes a plurality of data processing engines includes setting a first region among a plurality of regions of a host memory buffer allocated from an external host with a first data processing policy and setting a second region among the plurality of regions with a second data processing policy, performing an encoding operation on data to be stored in the first region, based on a first data processing engine corresponding to the first data processing policy, performing an encoding operation on data to be stored in the second region, based on a second data processing engine corresponding to the second data processing policy, and changing the first data processing policy of the first region to a third data processing policy based on a changed characteristic of the first region.