公开(公告)号：US20250078753A1

公开(公告)日：2025-03-06

申请号：US18732099

申请日：2024-06-03

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM ,  Bo Yong CHUNG

IPC: G09G3/3233

Abstract: An emission driver is disclosed that includes stages. Each of the stages includes a first circuit part configured to apply a first node voltage to a first node, a second circuit part configured to apply a second node voltage to a second node and connected to the first circuit part through a third node, a third circuit part configured to apply a third node voltage of the third node or a voltage higher than the third node voltage to a fourth node based on the first node voltage and the second node voltage, and a fourth circuit part configured to generate an emission signal based on the first node voltage and a fourth node voltage of the fourth node.

公开(公告)号：US20240127748A1

公开(公告)日：2024-04-18

申请号：US18486014

申请日：2023-10-12

Applicant: Samsung Display Co., LTD.

Inventor： Hyuk KIM ,  Jong Hee KIM ,  Doo Young LEE ,  Chang Soo LEE ,  Sang Uk LIM ,  Bo Yong CHUNG

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2320/043

Abstract: A display device includes a scan driver to supply scan signals to first and second scan lines, a data driver to supply a data signal to data lines, a sensor connected to sensing lines, and pixels including a light-emitting element, a driving transistor to control an amount of current supplied to the light-emitting element in response to a voltage of a first node, a switching transistor between a j-th data line and the first node, and including a gate electrode coupled to an i-th first scan line, and a sensing transistor coupled between a second node, which is between the light-emitting element and the driving transistor, and a k-th sensing line, and including a gate electrode coupled to an i-th second scan line, and wherein the sensor is to sense deterioration information of the light-emitting element in a state in which the switching and sensing transistors are turned on.

公开(公告)号：US20210074203A1

公开(公告)日：2021-03-11

申请号：US16881757

申请日：2020-05-22

Applicant: Samsung Display Co., LTD.

Inventor： Jong Hee KIM ,  Hyuk KIM ,  An Su LEE

IPC: G09G3/32

Abstract: A scan driver includes scan stages, an n-th scan stage of the scan stages includes a first driving circuit, a second driving circuit, and an output circuit. The first driving circuit controls a voltage of a first driving node, based on an input signal and a voltage of a second driving node. The second driving circuit controls the voltage of the second driving node, based on a second clock signal and a first voltage. The output circuit outputs a first clock signal as a scan signal and a carry signal, and outputs a second voltage as the scan signal and the carry signal. The first driving circuit includes a first transistor including a gate electrode electrically connected to the second driving node, one electrode electrically connected to an input line that provides the input signal, and another electrode electrically connected to the first driving node.

公开(公告)号：US20200066203A1

公开(公告)日：2020-02-27

申请号：US16366553

申请日：2019-03-27

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM

IPC: G09G3/32

Abstract: A display device includes a gate driver for applying scan signals and including a plurality of gate driving circuit blocks, and a data driver for applying a data voltage to data lines, wherein the gate driving circuit blocks respectively output a carry signal to be transmitted to a first input terminal of a subsequent gate driving circuit block based on a signal applied to a first control node through a first input terminal and a carry clock signal input to a carry clock input terminal, output a scan signal to a first scan line based on the signal applied to the first control node and a scan clock signal input to a first scan clock input terminal, and output a scan signal to a second scan line based on the signal applied to the first control node and a scan clock signal input to a second scan clock input terminal.

公开(公告)号：US20160240129A1

公开(公告)日：2016-08-18

申请号：US14920596

申请日：2015-10-22

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM ,  Ji-Sun KIM ,  Jun Hyun PARK ,  Young Wan SEO ,  Jae Keun LIM ,  Chong Chul CHAI

IPC: G09G3/20 ,  H03K19/0175

CPC classification number: G09G3/2092 ,  G09G2310/0286 ,  H03K19/017509

Abstract: A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.

Abstract translation: 根据本发明构思的示例性实施例的门电路包括多个级，每个级接收时钟信号并输出​​门信号和进位信号。 多个级中的一个包括第一晶体管和第一晶体管，第一晶体管的第一端子和控制端子彼此连接，并且前一级之前的级的进位信号被输入到第一端子和控制端子，第二晶体管的第二晶体管 前级的门信号被输入到第一端子，控制端子与第一晶体管的第二端子连接，输出端子连接到第一节点。

公开(公告)号：US20160210926A1

公开(公告)日：2016-07-21

申请号：US14862388

申请日：2015-09-23

Applicant: Samsung Display Co., Ltd.

Inventor： Tadashi AMINO ,  Jong Hee KIM ,  Masataka KANO ,  Jun Hyun PARK

IPC: G09G3/36 ,  H01L27/12

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G11C19/184 ,  G11C19/28 ,  H01L27/124 ,  H01L27/1255

Abstract: A Rate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.

Abstract translation: A速率驱动电路包括：多个阶段向栅线输出信号，该级包括一端和控制端连接的第一晶体管，一端与控制端与第一输入端连接，另一端 端部连接到第二节点，第二晶体管包括连接到与时钟输入端子连接的第一节点的控制端子，以及连接到第一输出端子的另一端，其一端连接到第一节点的第一电容器 第一节点，另一端连接到第二晶体管和第一输出端子的另一端，第三晶体管的一端连接到第一晶体管的另一端，另一端与第一节点连接 并且控制终端连接到第三节点。

公开(公告)号：US20240029659A1

公开(公告)日：2024-01-25

申请号：US18376340

申请日：2023-10-03

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM ,  Soo Yeon LEE

IPC: G09G3/3266 ,  G09G3/36

CPC classification number: G09G3/3266 ,  G09G3/3677 ,  G09G2310/08

Abstract: A scan driver for a display device may include a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage may include: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.

公开(公告)号：US20150287392A1

公开(公告)日：2015-10-08

申请号：US14456926

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM ,  Hyun Joon KIM ,  Kyoung Ju SHIN ,  Alexander WARD ,  Cheol-Gon LEE ,  Chong Chul CHAI

IPC: G09G5/18 ,  G09G3/36 ,  H03K17/693

CPC classification number: H03K17/693 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/06

Abstract: A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.

Abstract translation: 舞台包括：第一晶体管，包括施加时钟信号的输入端子和连接到第一节点的控制端子; 第一电容器，包括分别连接到第一节点的端子和第一晶体管的输出端子; 第二晶体管，包括连接到第一晶体管的输出端子的输入端子，连接到第二节点的控制端子和施加低电压的输出端子; 第三晶体管，包括连接到第二节点的输出端子，连接到第一节点的控制端子和施加低电压的输入端子; 以及第四晶体管，其包括连接到所述第一节点的输入端子和施加所述低电压的输出端子，其中所述第四晶体管根据下一级的输出信号被切换。

公开(公告)号：US20140160182A1

公开(公告)日：2014-06-12

申请号：US13939566

申请日：2013-07-11

Applicant: Samsung Display Co., Ltd.

Inventor： Seok Ha HONG ,  Dae-Gwang JANG ,  Sang Mi KIM ,  Ung Gyu MIN ,  Ji Myoung SEO ,  Bong Hyun YOU ,  Hyun Sik HWANG ,  Gi Geun KIM ,  Jong Hee KIM ,  Kyoung Won LEE

IPC: G09G5/00 ,  G09G5/02

CPC classification number: G09G5/00 ,  G09G3/3696 ,  G09G5/02 ,  G09G2300/08 ,  G09G2310/0213 ,  G09G2330/021 ,  G09G2330/028 ,  G09G2360/08

Abstract: A display device includes a display panel including a gate line, a data line, and a pixel connected to the gate line and the data line, a data driver connected to the data line, a gate driver connected to the gate line, and a signal controller controlling the data driver and the gate driver, wherein a circuits powering power source voltage that is normally used for driving the data driver is selectively not applied during a new-image blanking time when the signal controller is not supplying image data to the data driver.

Abstract translation: 显示装置包括：显示面板，包括栅极线，数据线，连接到栅极线和数据线的像素;连接到数据线的数据驱动器;连接到栅极线的栅极驱动器;以及信号 控制数据驱动器和栅极驱动器的控制器，其中，当信号控制器不向数据驱动器提供图像数据时，在新图像消隐时间期间，选择性地不应用为正常用于驱动数据驱动器的电源电压供电的电路 。

公开(公告)号：US20220036816A1

公开(公告)日：2022-02-03

申请号：US17503781

申请日：2021-10-18

Applicant: Samsung Display Co., LTD.

Inventor： Jong Hee KIM ,  Hyuk KIM ,  An Su LEE

IPC: G09G3/32

Abstract: A scan driver includes scan stages, an n-th scan stage of the scan stages includes a first driving circuit, a second driving circuit, and an output circuit. The first driving circuit controls a voltage of a first driving node, based on an input signal and a voltage of a second driving node. The second driving circuit controls the voltage of the second driving node, based on a second clock signal and a first voltage. The output circuit outputs a first clock signal as a scan signal and a carry signal, and outputs a second voltage as the scan signal and the carry signal. The first driving circuit includes a first transistor including a gate electrode electrically connected to the second driving node, one electrode electrically connected to an input line that provides the input signal, and another electrode electrically connected to the first driving node.