Abstract:
A display apparatus is disclosed that includes a substrate, a partition wall, and wiring. The substrate includes a display area and a peripheral area. The partition wall is arranged in the peripheral area. The wiring is arranged over the substrate extends from the display area to the peripheral area, and inserted into the partition wall or passes through the partition wall. The wiring includes at least one through hole.
Abstract:
A display apparatus is disclosed that includes a substrate, a partition wall, and wiring. The substrate includes a display area and a peripheral area. The partition wall is arranged in the peripheral area. The wiring is arranged over the substrate extends from the display area to the peripheral area, and inserted into the partition wall or passes through the partition wall. The wiring includes at least one through hole.
Abstract:
A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.
Abstract:
A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.
Abstract:
A display device, includes: a display panel; and a driving unit configured to receive image data, analyze the image data, and determine shapes of a plurality of pixel units making up the image, wherein the plurality of pixel units include a first pixel unit including a plurality of first sub-pixels or a second pixel unit including a plurality of second sub-pixels and having a shape different from a shape of the first pixel unit, and wherein the first sub-pixels and the second sub-pixels include a 1-1st color sub-pixel configured to emit a first color, a 1-2nd color sub-pixel configured to emit the first color, a second color sub-pixel configured to emit a second color, the second color being different from the first color, and a third color sub-pixel configured to emit a third color, the third color being different from the first color and the second color.
Abstract:
A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.
Abstract:
A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.
Abstract:
A pixel includes: a first driving transistor and a second driving transistor; a first select transistor connected between a gate of the first driving transistor and a gate node; and a second select transistor connected between a gate of the second driving transistor and the gate node.
Abstract:
A display device may include a driving transistor disposed in a display area, a test transistor disposed in a peripheral area adjacent to the display area, and a resistance line disposed in the peripheral area, electrically connected to the test transistor and including a metal oxide.
Abstract:
A display device may include a driving transistor disposed in a display area, a test transistor disposed in a peripheral area adjacent to the display area, and a resistance line disposed in the peripheral area, electrically connected to the test transistor and including a metal oxide.