Abstract:
A driving unit of display panel includes a data driving part, a timing controlling part and a gate driving part. The data driving part is configured to receive reference image data and includes a first data driving circuit part having a first channel outputting a first reference data signal based on the reference image data and a k-th channel outputting a k-th reference data signal based on the reference image data. The timing controlling part is configured to detect a time difference between the first reference data signal and the k-th reference data signal. The gate driving part is configured to output a gate signal to each of gate lines. By delaying data signals based on the gate signal delay caused by long line load and RC delay, the present invention may improve display quality of a display device.
Abstract:
A display device includes a display panel including gate lines, data lines, and pixels each connected to a corresponding gate line and a corresponding data line, a gate driver configured to drive the gate lines, a data driver configured to drive the data lines, and a timing controller configured to generate control signals to control the data driver and to apply a vertical synchronization start signal including a first pulse, a second pulse, a first gate pulse signal, and a second gate pulse signal to the gate driver. The gate driver applies gate driving signals to the gate lines to pre-charge the pixels in response to the first pulse of the vertical synchronization start signal and the first gate pulse signal, and to main-charge the pixels in response to the second pulse of the vertical synchronization start signal and the second gate pulse signal.
Abstract:
A display panel driving apparatus, including a gate driving part configured to output a gate signal to gate lines of a display panel, and a data driving part configured to output a data signal to a data line of the display panel, including a digital-analog converter, wherein the digital-analog converter is configured to convert a common voltage control data of digital format to a common voltage control voltage of analog format.
Abstract:
A display device includes a display panel including a plurality of pixels, a gate driver configured to provide gate signals to the plurality of pixels, a data driver configured to provide data signals to the plurality of pixels, a correction data memory configured to store mura correction data, and a controller configured to control the gate driver and the data driver. The controller includes a pattern detection block configured to detect a set pattern in input image data, and a mura correction block configured to perform a mura correction operation that corrects the input image data based on the mura correction data in response to the set pattern not being detected, and to not perform the mura correction operation in accordance with the set pattern being detected.
Abstract:
A display device includes a display panel and a signal controller. The signal controller receives an input signal and controls an operation of the display panel. The signal controller controls the display panel to display different images according to different types of a fail when determining the fail in the input signal.
Abstract:
A display apparatus includes a display panel, a position detector, a driving controller, a gate driver and a data driver. The display panel is configured to display an image. The position detector is configured to determine a position of a user. The driving controller is configured to generate an overdriving value according to a grayscale value of previous frame data and a grayscale value of present frame data. The gate driver is configured to output gate signals to the display panel. The data driver is configured to output data voltages to the display panel based on the overdriving value.
Abstract:
An apparatus for monitoring pixel data includes a multiplexer configured to select pixel data applied to at least one of function blocks which is configured to convert the pixel data provided from an external device and adjust characteristics of a display device, a monitoring module configured to store the pixel data selected by the multiplexer, and an analyzing module configured to output a location selection signal to the multiplexer which provides the monitoring module with the pixel data based on the location selection signal, to read out the pixel data stored in the monitoring module by applying a pixel position signal to the monitoring module, and to analyze a variation of the read out pixel data.
Abstract:
A timing controller for a display apparatus includes a dithering unit outputting a first signal in which bit widths of image signals are reduced, an image pattern detector detecting an image pattern of the image signals and outputting a dithering off signal corresponding to the detected image pattern, a dithering selector receiving the first signal and converts the first signal to a second signal in response to the dithering off signal, and a response time compensator generating a present image signal from the second signal and compensates a liquid crystal response time in accordance with a difference between the present image signal and a first previous image signal to output a data signal.
Abstract:
A driving unit of display panel includes a data driving part, a timing controlling part and a gate driving part. The data driving part is configured to receive reference image data and includes a first data driving circuit part having a first channel outputting a first reference data signal based on the reference image data and a k-th channel outputting a k-th reference data signal based on the reference image data. The timing controlling part is configured to detect a time difference between the first reference data signal and the k-th reference data signal. The gate driving part is configured to output a gate signal to each of gate lines. By delaying data signals based on the gate signal delay caused by long line load and RC delay, the present invention may improve display quality of a display device.
Abstract:
A display apparatus includes a plurality of pixels connected to a plurality of gate lines and a plurality of data lines and a timing controller, in which each pixel includes a first sub-pixel and a second sub-pixel. In such a display apparatus, the timing controller provides the first sub-pixel and the second sub-pixel with a first data signal and a second data signal corresponding to one of a high gray scale curve and a low gray scale curve, alternately every frame, when the image signal is a first type of image signal, and the timing controller provides the first sub-pixel with a first data signal corresponding to the high gray scale curve and the second sub-pixel with a second data signal corresponding to the low gray scale curve when the image signal is a first type of image signal.