Abstract:
A display device includes a display panel including gate lines, data lines, and pixels each connected to a corresponding gate line and a corresponding data line, a gate driver configured to drive the gate lines, a data driver configured to drive the data lines, and a timing controller configured to generate control signals to control the data driver and to apply a vertical synchronization start signal including a first pulse, a second pulse, a first gate pulse signal, and a second gate pulse signal to the gate driver. The gate driver applies gate driving signals to the gate lines to pre-charge the pixels in response to the first pulse of the vertical synchronization start signal and the first gate pulse signal, and to main-charge the pixels in response to the second pulse of the vertical synchronization start signal and the second gate pulse signal.
Abstract:
A display apparatus includes a first interpolator configured to generate first correction data for a first polarity corresponding to an input data using a first look up table which stores correction data for the first polarity compensating for a luminance difference between the first polarity and a second polarity opposite to the first polarity of a data voltage for the sub pixel, a first delay compensator configured to apply a correction value to the first correction data for the first polarity and generate second correction data for the first polarity, the correction value compensating for an RC delay based on a pixel position corresponding to the input data.
Abstract:
A display device includes a display panel including a plurality of pixels, a gate driver configured to provide gate signals to the plurality of pixels, a data driver configured to provide data signals to the plurality of pixels, a correction data memory configured to store mura correction data, and a controller configured to control the gate driver and the data driver. The controller includes a pattern detection block configured to detect a set pattern in input image data, and a mura correction block configured to perform a mura correction operation that corrects the input image data based on the mura correction data in response to the set pattern not being detected, and to not perform the mura correction operation in accordance with the set pattern being detected.
Abstract:
In a method of operating a display device supporting a variable frame mode, frame data are received during a constant active period of a frame period including the active period and a variable blank period, the received frame data are written to a frame memory in the active period, the received frame data are outputted to a data driver in the active period to display an image based on the received frame data, a time of the variable blank period is counted, and, when the time of the variable blank period reaches a predetermined threshold blank time, the frame data stored in the frame memory are outputted to the data driver in the variable blank period to display an image based on the frame data stored in the frame memory.
Abstract:
An apparatus for monitoring pixel data includes a multiplexer configured to select pixel data applied to at least one of function blocks which is configured to convert the pixel data provided from an external device and adjust characteristics of a display device, a monitoring module configured to store the pixel data selected by the multiplexer, and an analyzing module configured to output a location selection signal to the multiplexer which provides the monitoring module with the pixel data based on the location selection signal, to read out the pixel data stored in the monitoring module by applying a pixel position signal to the monitoring module, and to analyze a variation of the read out pixel data.
Abstract:
A display apparatus includes a plurality of pixels connected to a plurality of gate lines and a plurality of data lines and a timing controller, in which each pixel includes a first sub-pixel and a second sub-pixel. In such a display apparatus, the timing controller provides the first sub-pixel and the second sub-pixel with a first data signal and a second data signal corresponding to one of a high gray scale curve and a low gray scale curve, alternately every frame, when the image signal is a first type of image signal, and the timing controller provides the first sub-pixel with a first data signal corresponding to the high gray scale curve and the second sub-pixel with a second data signal corresponding to the low gray scale curve when the image signal is a first type of image signal.