公开(公告)号：US20130075763A1

公开(公告)日：2013-03-28

申请号：US13629780

申请日：2012-09-28

Applicant: Samsung Display Co., Ltd.

Inventor： Ki-Hun JEONG ,  Woongkwon KIM ,  Jung Suk BANG ,  Daecheol KIM ,  Sungryul KIM ,  ByeongHoon CHO ,  Sungjin MUN ,  Kun-Wook HAN

IPC: H01L33/48 ,  H01L33/00

CPC classification number: H01L33/48 ,  G02F2001/13312 ,  G06F3/0412 ,  G06F2203/04103 ,  G09G3/00 ,  H01L33/005

Abstract: A display apparatus includes a first substrate including a plurality of pixels, and a second substrate facing the first substrate, the second substrate comprising a sensor area and a peripheral area, the sensor area comprising a plurality of sensors. The second substrate includes an insulating layer, and a plurality of lines disposed on the insulating layer corresponding to the peripheral area and connected to the sensors. A void is formed in the insulating layer between two adjacent lines of the plurality of lines at a boundary of the sensor area and the peripheral area.

Abstract translation: 显示装置包括包括多个像素的第一基板和面对第一基板的第二基板，第二基板包括传感器区域和周边区域，传感器区域包括多个传感器。 第二基板包括绝缘层，以及设置在绝缘层上的与周边区域对应并连接到传感器的多条线。 在传感器区域和周边区域的边界处，在多条线路的两条相邻线路之间的绝缘层中形成空穴。

公开(公告)号：US20170285390A1

公开(公告)日：2017-10-05

申请号：US15471892

申请日：2017-03-28

Applicant: Samsung Display Co., Ltd

Inventor： Sungjin MUN ,  Namwook LEE ,  Kihun JEONG ,  Xinxing LI ,  Hyeongjun JIN

IPC: G02F1/1345 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1339 ,  G02F1/1335

CPC classification number: G02F1/13452 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/1339 ,  G02F1/13394 ,  G02F1/13458 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1248

Abstract: A display device includes: a first substrate including a display area and a non-display area; a gate line in the display area and a gate pad in the non-display area, the gate line extending in a first direction; a data line in the display area, the data line extending in a second direction intersecting the first direction; a thin film transistor at an intersection point among the gate line and the data line; a step-difference pattern on the gate pad; and a protective layer including a first protective layer on the thin film transistor and a second protective layer on the step-difference pattern and the gate pad. The second protective layer has a height less than a height of the first protective layer.