公开(公告)号：US20240331608A1

公开(公告)日：2024-10-03

申请号：US18732585

申请日：2024-06-03

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20 ,  G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/2092 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2310/0202 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20230245612A1

公开(公告)日：2023-08-03

申请号：US18132704

申请日：2023-04-10

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G2310/08 ,  G09G2310/0267 ,  G09G2310/0275

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20220005402A1

公开(公告)日：2022-01-06

申请号：US17478825

申请日：2021-09-17

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20200372851A1

公开(公告)日：2020-11-26

申请号：US16875682

申请日：2020-05-15

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.