公开(公告)号：US20240282248A1

公开(公告)日：2024-08-22

申请号：US18530609

申请日：2023-12-06

Applicant: Samsung Display Co., Ltd.

Inventor： EOK SU KIM ,  JONGDO KEUM ,  TAESANG KIM

IPC: G09G3/32 ,  G09G3/3266

CPC classification number: G09G3/32 ,  G09G3/3266 ,  G09G2310/0267

Abstract: A scan driving circuit includes multiple stages. A j-th stage of the stages includes a buffer part electrically connected to an output terminal that operates in response to a potential of a first control node, a holding part electrically connected to the output terminal that operates in response to a potential of a second control node, and an inverter part electrically connected to the first and second control nodes that controls the potentials of the first and second nodes. The inverter part includes a control transistor including a gate electrically connected to the first control node, and a drain electrically connected to a first voltage terminal that receives a first low voltage or a second voltage terminal that receives a second low voltage. The control transistor includes a dummy gate that receives a low voltage lower than or equal to the first and second low voltages.

公开(公告)号：US20240257724A1

公开(公告)日：2024-08-01

申请号：US18513917

申请日：2023-11-20

Applicant: Samsung Display Co., LTD.

Inventor： EOK SU KIM ,  JONGDO KEUM ,  TAESANG KIM

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/0267 ,  G09G2310/0294 ,  G09G2310/061 ,  G09G2310/08

Abstract: A gate driving circuit includes: a first pull-up control circuit, a pull-up circuit, a pull-down circuit and an inverting circuit. The first pull-up control circuit applies a previous carry signal which is one of carry signals of previous stages to a first control node in response to the previous carry signal. The pull-up circuit outputs a gate clock signal as a gate output signal in response to a signal of the first control node. The pull-down circuit outputs a second low voltage as the gate output signal in response to a first next carry signal which is one of carry signals of next stages. The inverting circuit outputs one of a first signal and a first low voltage to a third control node in response to the first signal and a signal of a second control node.

公开(公告)号：US20240049544A1

公开(公告)日：2024-02-08

申请号：US18297052

申请日：2023-04-07

Applicant: Samsung Display Co., LTD.

Inventor： Joon Seok PARK ,  JONGDO KEUM ,  Hyoung Do KIM ,  Yun Yong NAM ,  Chul Won PARK ,  Kilim HAN

IPC: H10K59/131 ,  H10K59/12 ,  H10K59/124

CPC classification number: H10K59/1315 ,  H10K59/1201 ,  H10K59/124

Abstract: A display device includes: a substrate; a conductive pattern layer disposed on the substrate; a buffer layer disposed on the conductive pattern layer; an active pattern layer disposed on the buffer layer and including a channel region and a conductive region adjacent to the channel region; an insulating pattern layer disposed on the channel region; an oxide pattern layer disposed on the insulating pattern layer; a gate electrode disposed on the oxide pattern layer; and a connecting member electrically connected to the conductive pattern layer and the conductive region. The connecting member and the oxide pattern layer include a same material.