公开(公告)号：US20240349547A1

公开(公告)日：2024-10-17

申请号：US18619160

申请日：2024-03-28

Applicant: Samsung Display Co., Ltd. ,  IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

Inventor： EUN HYUN KIM ,  Gwang Bok KIM ,  JUN HYUNG LIM ,  Jae Kyeong JEONG

IPC: H10K59/124 ,  H01L29/24 ,  H01L29/786 ,  H10K59/12

CPC classification number: H10K59/124 ,  H01L29/24 ,  H01L29/7869 ,  H10K59/1201

Abstract: A display device is disclosed that includes a base substrate, an organic light emitting element disposed on the base substrate, an insulating layer disposed on the base substrate and containing silicon oxide, and a thin film transistor disposed on the base substrate and electrically connected to the organic light emitting element, wherein the thin film transistor includes a semiconductor pattern disposed on the base substrate and including a channel area in contact with the insulating layer, and a gate electrode overlapping the channel area on a plane, wherein the semiconductor pattern contains indium gallium zinc tin oxide.

公开(公告)号：US20170062622A1

公开(公告)日：2017-03-02

申请号：US15235201

申请日：2016-08-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： HYE HYANG PARK ,  EUN HYUN KIM ,  TAE YOUNG KIM ,  YEON KEON MOON ,  SHIN HYUK YANG

IPC: H01L29/786 ,  H01L29/49 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78678 ,  H01L29/78696

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes a substrate and a gate electrode disposed on the substrate. A gate insulating layer is disposed on the substrate and covers the gate electrode. A semiconductor layer is disposed on the gate insulating layer and includes a channel region, a source region, and a drain region. The source and drain regions are separated from each other by the channel region. An etch stopper is disposed on the semiconductor layer. A passivation layer is disposed on the semiconductor layer and covers the etch stopper. A source electrode and a drain electrode are disposed on the passivation layer and are respectively connected to the source region and the drain region. The passivation layer includes a first sub-passivation layer including aluminum oxide (AlOx).

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括基板和设置在基板上的栅电极。 栅极绝缘层设置在基板上并覆盖栅电极。 半导体层设置在栅极绝缘层上，并且包括沟道区，源极区和漏极区。 源区和漏区通过沟道区彼此分离。 在半导体层上设置蚀刻停止层。 钝化层设置在半导体层上并覆盖蚀刻停止层。 源电极和漏电极设置在钝化层上，分别连接到源极区和漏极区。 钝化层包括包括氧化铝（AlOx）的第一子钝化层。

公开(公告)号：US20230189566A1

公开(公告)日：2023-06-15

申请号：US18079115

申请日：2022-12-12

Applicant: Samsung Display Co., Ltd.

Inventor： SANGWOO SOHN ,  YEON KEON MOON ,  EUN HYUN KIM ,  SEUNGHO YANG ,  JUN HYUNG LIM ,  Hyunjun JEONG

IPC: H10K59/121 ,  H10K59/12 ,  H10K71/00 ,  H01L29/786

CPC classification number: H10K59/1213 ,  H10K59/1201 ,  H10K71/00 ,  H01L29/7869

Abstract: A display device includes insulating layers, a light-emitting element, and a pixel circuit electrically connected to the light-emitting element. The pixel circuit includes a first transistor. The first transistor includes a metal oxide semiconductor pattern including a source region, a drain region and a channel region disposed between the source region and the drain region, a first gate disposed on the metal oxide semiconductor pattern and overlapping the channel region in a plan view, and a metal oxide pattern disposed on the first gate.

公开(公告)号：US20220123075A1

公开(公告)日：2022-04-21

申请号：US17358518

申请日：2021-06-25

Applicant: Samsung Display Co., Ltd.

Inventor： EUN HYUN KIM ,  JAYBUM KIM ,  KYOUNG SEOK SON ,  SUNHEE LEE ,  JUN HYUNG LIM

IPC: H01L27/32 ,  H01L51/52 ,  G06F1/16

Abstract: A display device includes a display area and a functional area defining a through-portion therein. At least a portion of the functional area is surrounded by the display area. The display device includes an insulation layer disposed on a base substrate and defining a disconnection portion in the functional area, a pixel array disposed on the base substrate in the display area, and a mask pattern including a metal oxide and extending along the disconnection portion in a plan view.