公开(公告)号：US20170084708A1

公开(公告)日：2017-03-23

申请号：US15369008

申请日：2016-12-05

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Bon-Yong KOO ,  Soo Jin PARK ,  Jong-Moon PARK ,  Yong Hee LEE ,  Jong-Hyuk LEE ,  Duc-Han CHO

IPC: H01L29/417 ,  H01L27/12

CPC classification number: H01L29/41733 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/156 ,  H01L29/41775

Abstract: A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.

公开(公告)号：US20160171950A1

公开(公告)日：2016-06-16

申请号：US14742915

申请日：2015-06-18

Applicant: Samsung Display Co., Ltd.

Inventor： Duc-Han CHO ,  Kang Nam KIM ,  Beom Jun KIM ,  You Mee HYUN

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/287

Abstract: A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.

Abstract translation: 显示装置包括：多个像素; 连接到所述多个像素的多个栅极线; 连接到栅极线的栅极线的输出端子; 连接到第一节点的第一晶体管，第一时钟信号输入端和输出端; 连接到第二时钟信号输入端子的第二晶体管，低电平电源电压和输出端子; 连接到第二节点的第三晶体管，低电平电源电压和第一节点; 连接到第一正向输入端子的第四晶体管，低电平电源电压和第二节点; 以及与第一反向输入端子，低电平电源电压和第二节点连接的第五晶体管。

公开(公告)号：US20140191238A1

公开(公告)日：2014-07-10

申请号：US14099977

申请日：2013-12-08

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Bon-Yong KOO ,  Soo Jin PARK ,  Jong-Moon PARK ,  Yong Hee LEE ,  Jong-Hyuk LEE ,  Duc-Han CHO

IPC: H01L27/12 ,  H01L27/15

CPC classification number: H01L29/41733 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/156 ,  H01L29/41775

Abstract: A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.

Abstract translation: 薄膜晶体管阵列面板包括在延伸方向上延伸的栅极线，并且包括从其延伸的栅极和虚拟栅电极; 源电极和在其第一端包括漏极的单个漏极构件和在其相对的第二端处的虚设漏电极。 漏电极相对于栅电极面对源电极，虚设漏电极与虚拟栅电极重叠。 漏极和虚设漏电极分别包括在延伸方向上具有预定宽度的多个第一和第二区域。 第二区域包括与延伸方向形成约0度至约90度的角度的边缘，并且多个第二区域中的至少一个的平面区域与剩余的第二区域的平面区域不同。