公开(公告)号：US08780032B2

公开(公告)日：2014-07-15

申请号：US14053229

申请日：2013-10-14

Applicant: Samsung Display Co., Ltd.

Inventor： Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-Jin Jeon

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2320/0223

Abstract: In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Abstract translation: 在具有显示面板的显示面板和显示装置中，显示面板包括阵列和相对的基板。 阵列基板包括显示器和外围区域。 栅极和源极线形成在显示区域中。 在周边区域中形成栅极驱动部分和第一和第二时钟线。 栅极驱动部分将栅极信号输出到栅极线。 第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。 相对的衬底与阵列衬底组合并且包括公共电极层。 公共电极层具有图案化以暴露第一和第二时钟线的开口部分。 第一和第二时钟线的暴露部分具有基本上相同的面积。 因此，可以使门信号的延迟最小化并且可以防止门信号的失真。

公开(公告)号：US09552759B2

公开(公告)日：2017-01-24

申请号：US14731704

申请日：2015-06-05

Applicant: Samsung Display Co., Ltd.

Inventor： Sang-Jin Jeon ,  Il-Gon Kim ,  Hee-Rim Song

IPC: G06F3/038 ,  G09G3/20

CPC classification number: G09G3/2085 ,  G09G3/20 ,  G09G2300/026 ,  G09G2300/0408 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2310/0202 ,  G09G2310/0278 ,  G09G2310/0281 ,  G09G2310/08 ,  G09G2320/0247

Abstract: A display apparatus includes a display panel including a driving part arranged along one side of the display panel, the display panel including a plurality of first gate lines that zigzag across the display in a diagonal direction between the first and second directions by alternately extending in the first and the second directions. The display device includes a first display area and a second display area, pixels within the first display area always receiving gate signals from a driving part connected to an end of the first gate lines. Within the second display area, a second gate lines extending in the first direction may be electrically connected to the first gate lines that relay gate signals to the first gate lines. This results in a reduced peripheral area of the display area, so that many displays can be combined together to produce a single image.

Abstract translation: 显示装置包括：显示面板，包括沿着显示面板的一侧布置的驱动部，所述显示面板包括多个第一栅极线，所述多个第一栅极线在所述第一和第二方向之间沿对角线方向在所述显示器之间交替延伸 第一和第二个方向。 显示装置包括第一显示区域和第二显示区域，第一显示区域内的像素总是从连接到第一栅极线的端部的驱动部分接收栅极信号。 在第二显示区域内，沿第一方向延伸的第二栅极线可以电连接到将栅极信号中继到第一栅极线的第一栅极线。 这导致显示区域的减少的外围区域，使得许多显示器可以组合在一起以产生单个图像。

公开(公告)号：US09355741B2

公开(公告)日：2016-05-31

申请号：US14276801

申请日：2014-05-13

Applicant: Samsung Display Co., LTD.

Inventor： Sang-Jin Jeon ,  Jun-Ki Jeong ,  Se-Hyoung Cho

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286

Abstract: A gate drive circuit includes a shift register having a plurality of stages, in which an n-th stage (‘n’ is a natural number) of the plurality of stages is connected to at least one subsequent stage. The n-th stage includes a pull-up part configured to output a high voltage of an n-th gate signal using a high voltage of a clock signal as in response to a high voltage of a control node, a control pull-down part configured to pull-down a voltage of the control node into a low voltage in response to a carry signal outputted from at least one of next stages of the n-th stage and receiving a back-bias voltage corresponding to the low voltage, and a carry part configured to output the high voltage of the clock signal as an n-th carry signal in response to a high voltage of the control node.

Abstract translation: 栅极驱动电路包括具有多个级的移位寄存器，其中多级的第n级（'n'是自然数）连接到至少一个后级。 第n级包括上拉部分，其配置为响应于控制节点的高电压，使用时钟信号的高电压输出第n门信号的高电压;控制下拉部分 被配置为响应于从第n级的下一级中的至少一级输出的进位信号将控制节点的电压下拉到低电压并且接收与低电压相对应的反偏压，以及 携带部件被配置成响应于控制节点的高电压而输出时钟信号的高电压作为第n进位信号。