公开(公告)号：US20240329098A1

公开(公告)日：2024-10-03

申请号：US18615233

申请日：2024-03-25

Applicant: STMicroelectronics International N.V.

Inventor： Roberto TIZIANI ,  Francesca DE VITI

IPC: G01R15/20 ,  G01R19/00 ,  H01L21/8234 ,  H01L23/31

CPC classification number: G01R15/207 ,  G01R15/202 ,  G01R19/0092 ,  H01L21/8234 ,  H01L23/3121

Abstract: An insulating encapsulation encapsulates a semiconductor die having an integrated Hall current sensor configured to measure an electric current flowing adjacent an active surface of the semiconductor die. An electrically conductive trace is embedded in the insulating encapsulation. First electrically conductive formations extend through the insulating encapsulation towards opposed ends of the electrically conductive trace. The first electrically conductive formations are configured to cause an electrical current subject to measurement to flow in a current flow path through the electrically conductive trace. Second electrically conductive formations extend through the insulating encapsulation towards the active surface of the semiconductor die. The second electrically conductive formations are configured to activate the Hall current sensor integrated in the semiconductor die.

公开(公告)号：US20240363501A1

公开(公告)日：2024-10-31

申请号：US18634663

申请日：2024-04-12

Applicant: Shenzhen STS Microelectronics Co., Ltd ,  STMicroelectronics International N.V.

Inventor： Qian LIU ,  Roberto TIZIANI

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49562 ,  H01L23/3675 ,  H01L23/49531 ,  H01L24/29 ,  H01L24/37 ,  H01L25/0652 ,  H01L2224/29005 ,  H01L2224/29022 ,  H01L2224/3702 ,  H01L2224/37147 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/13091

Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming semiconductor package and a power module. For example, there is provided a semiconductor package. The semiconductor package may comprise a chip level having a first side and a second side opposite to the first side, wherein the chip level comprises a plurality of power transistors and each power transistor is provided with a source and a gate at the first side. Besides, the semiconductor package may also comprise a first conductive level positioned on the first side and comprising a gate connection portion electrically connected with the gate and a source connection portion electrically connected with the source. The semiconductor package further comprises a second conductive level comprising a gate lead-out portion electrically connected with the gate connection portion and a source lead-out portion electrically connected with the source connection portion, wherein the first conductive level is positioned between the second conductive level and the chip level. Embodiments of the present disclosure may enhance the working performance of the product by improving consistency of conductive paths from the gate and the source of each power transistor to corresponding points.