公开(公告)号：US20250111875A1

公开(公告)日：2025-04-03

申请号：US18815356

申请日：2024-08-26

Applicant: STMicroelectronics International N.V.

Inventor： Sant Swaroop SHRIVASTAVA ,  Hitesh CHAWLA ,  Mohd Javed IKHLAS ,  Sachin GULYANI

IPC: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: A memory system includes a memory array with first dummy read cells that discharge a dummy bit line, each of the first dummy read cells including a transistor coupled between the dummy bit line and a first ground node that is connected to a ground reference. Second dummy read cells discharge the dummy bit line, each of the dummy read cells including a transistor coupled between the dummy bit line and a second ground node. The dummy read cells cooperate to discharge the dummy bit line in a dummy read operation to provide a self-timing signal. Read circuitry retrieves data from a selected row in the memory array during a read operation, in response to the self-timing signal. Ground generation circuitry connects the second ground node to the ground reference or allows the second ground to float, based upon a control signal.