公开(公告)号：US20240332162A1

公开(公告)日：2024-10-03

申请号：US18616696

申请日：2024-03-26

Applicant: STMicroelectronics International N.V.

Inventor： William THIES ,  Gilles GASIOT ,  Andrea PAGANINI ,  Jerome DEROO ,  Matteo REPOSSI

IPC: H01L23/522 ,  H03H7/01

CPC classification number: H01L23/5223 ,  H01L23/5225 ,  H03H7/0115

Abstract: A device includes a substrate and an interconnection network on the substrate. The interconnection network includes at least a first level, at least a second level and a third level. The first level includes one or more capacitors. The third level includes a metallic shield. The second level is positioned between the first level and the substrate. The capacitors of the first level are entirely separated from the substrate by the shield. The second level is located between the first and third levels.

公开(公告)号：US20250141653A1

公开(公告)日：2025-05-01

申请号：US18920028

申请日：2024-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Matteo COLOMBO ,  Augusto Andrea ROSSI ,  Jerome DEROO

IPC: H04L7/00 ,  H03L7/085 ,  H04L7/033 ,  H04L7/04

Abstract: An electronic digital system includes a digital core and a Serializer Deserializer module. A FIFO device of the core reads and writes on a set of buses coupled to said Serializer Deserializer module. The Serializer Deserializer module transmits data read from the FIFO architecture device on a set of buses as a corresponding serial signals transmitted by transmitters. The serial signals and corresponding transmitters are logically grouped. The transmitters include PLL circuits generating PLL clocks, using as reference a cluster transmitter reference clock common, to a respective cluster of transmitters controlling a frequency of serialization operation and low frequency clocks obtained by the PLL clocks according to one or more groups corresponding to group of buses.