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公开(公告)号：US20140189169A1
公开(公告)日：2014-07-03
申请号：US13731278
申请日：2012-12-31
Applicant: SILICON LABORATORIES INC.
Inventor： Timothy E. Litch , Paul I. Zavalney
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: An apparatus includes an integrated circuit that includes a processing core and a direct memory access (DMA) engine. The DMA engine is adapted to process descriptors to control DMA communications. The descriptors contain data indicating communication endpoints that are associated with the DMA communications. The DMA engine is adapted to use other data contained in at least one of the descriptors to control branching of descriptor execution among multiple execution paths.
Abstract translation: 一种装置包括集成电路，其包括处理核心和直接存储器存取（DMA）引擎。 DMA引擎适用于处理描述符以控制DMA通信。 描述符包含指示与DMA通信相关联的通信端点的数据。 DMA引擎适于使用包含在至少一个描述符中的其他数据来控制多个执行路径之间的描述符执行的分支。
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公开(公告)号：US20150006765A1
公开(公告)日：2015-01-01
申请号：US13928487
申请日：2013-06-27
Applicant: SILICON LABORATORIES INC.
Inventor： Timothy E. Litch , Paul I. Zavalney , Paul Zucker
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: A method includes processing descriptors to control a direct memory access (DMA) channel. The method includes synchronizing at least part of the processing, which includes processing a first descriptor of the descriptors to cause the execution to selectively pause based on a trigger value.
Abstract translation: 一种方法包括处理描述符以控制直接存储器存取（DMA）通道。 该方法包括同步处理的至少一部分，其包括处理描述符的第一描述符，以使执行基于触发值选择性地暂停。
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公开(公告)号：US10169256B2
公开(公告)日：2019-01-01
申请号：US14169527
申请日：2014-01-31
Applicant: Silicon Laboratories Inc.
Inventor： Timothy E. Litch , Paul Zucker , William G. Durbin
Abstract: A method includes receiving a plurality of requests to perform accesses for associated DMA channels and arbitrating the requests. The arbitration includes selectively granting a given request of the plurality of requests based at least in part on an associated fixed priority of the request and an associated priority weighting of the request. The priority weighting regulates which request or requests of the plurality of requests are considered at a given time.
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Patent Agency Ranking
公开(公告)号：US09256558B2
公开(公告)日：2016-02-09
申请号：US13928487
申请日：2013-06-27
Applicant: SILICON LABORATORIES INC.
Inventor： Timothy E. Litch , Paul I. Zavalney , Paul Zucker
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: A method includes processing descriptors to control a direct memory access (DMA) channel. The method includes synchronizing at least part of the processing, which includes processing a first descriptor of the descriptors to cause the execution to selectively pause based on a trigger value.
Abstract translation: 一种方法包括处理描述符以控制直接存储器存取（DMA）通道。 该方法包括同步处理的至少一部分，其包括处理描述符的第一描述符，以使执行基于触发值选择性地暂停。
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公开(公告)号：US20150220460A1
公开(公告)日：2015-08-06
申请号：US14169527
申请日：2014-01-31
Applicant: Silicon Laboratories Inc.
Inventor： Timothy E. Litch , Paul Zucker , William G. Durbin
CPC classification number: G06F13/1621 , G06F13/30
Abstract: A method includes receiving a plurality of requests to perform accesses for associated DMA channels and arbitrating the requests. The arbitration includes selectively granting a given request of the plurality of requests based at least in part on an associated fixed priority of the request and an associated priority weighting of the request. The priority weighting regulates which request or requests of the plurality of requests are considered at a given time.
Abstract translation: 一种方法包括接收多个请求以执行相关DMA通道的访问并仲裁请求。 仲裁包括至少部分地基于请求的相关联的固定优先级和请求的相关联的优先级加权来选择性地授予多个请求的给定请求。 优先权加权调节在给定时间考虑多个请求的哪个请求或请求。
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公开(公告)号：US09251107B2
公开(公告)日：2016-02-02
申请号：US13928506
申请日：2013-06-27
Applicant: SILICON LABORATORIES INC.
Inventor： Timothy E. Litch , Paul Zucker
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: A method includes processing a direct memory access (DMA) descriptor in a DMA controller. The method includes storing first data of the DMA descriptor at an address that is identified by second data of the DMA descriptor.
Abstract translation: 一种方法包括处理DMA控制器中的直接存储器访问（DMA）描述符。 该方法包括将DMA描述符的第一数据存储在由DMA描述符的第二数据标识的地址处。
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7.发明授权System and method for regulating direct memory access descriptor among multiple execution paths by using a link to define order of executions 有权通过使用链接来定义执行顺序来调节多个执行路径中的直接存储器访问描述符的系统和方法公开(公告)号：US09164936B2
公开(公告)日：2015-10-20
申请号：US13731278
申请日：2012-12-31
Applicant: Silicon Laboratories Inc.
Inventor： Timothy E. Litch , Paul I. Zavalney
CPC classification number: G06F13/28
Abstract: An apparatus includes an integrated circuit that includes a processing core and a direct memory access (DMA) engine. The DMA engine is adapted to process descriptors to control DMA communications. The descriptors contain data indicating communication endpoints that are associated with the DMA communications. The DMA engine is adapted to use other data contained in at least one of the descriptors to control branching of descriptor execution among multiple execution paths.
Abstract translation: 一种装置包括集成电路，其包括处理核心和直接存储器存取（DMA）引擎。 DMA引擎适用于处理描述符以控制DMA通信。 描述符包含指示与DMA通信相关联的通信端点的数据。 DMA引擎适于使用包含在至少一个描述符中的其他数据来控制多个执行路径之间的描述符执行的分支。
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公开(公告)号：US20150006768A1
公开(公告)日：2015-01-01
申请号：US13928506
申请日：2013-06-27
Applicant: SILICON LABORATORIES INC.
Inventor： Timothy E. Litch , Paul Zucker
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: A method includes processing a direct memory access (DMA) descriptor in a DMA controller. The method includes storing first data of the DMA descriptor at an address that is identified by second data of the DMA descriptor.
Abstract translation: 一种方法包括处理DMA控制器中的直接存储器访问（DMA）描述符。 该方法包括将DMA描述符的第一数据存储在由DMA描述符的第二数据标识的地址处。
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