公开(公告)号：US20240310437A1

公开(公告)日：2024-09-19

申请号：US18604021

申请日：2024-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seaeun Park ,  Saeeun Kim

IPC: G01R31/3177 ,  G11C16/04

CPC classification number: G01R31/3177 ,  G11C16/0483

Abstract: An integrated circuit includes: (i) a first block containing a first wrapper and a first area of circuit elements isolated by the first wrapper, (ii) a core logic circuit containing a target block, which includes a second wrapper and a second area of circuit elements isolated by the second wrapper, and a third wrapper and a third area of circuit elements isolated by the third wrapper, and (iii) a second block containing a fourth wrapper and a fourth area isolated by the fourth wrapper. The second wrapper is connected in series with the first wrapper, and is configured to support performance of a test operation on the second area. The third wrapper is connected in series with the fourth wrapper, and is configured to support performance of a test operation on the third area.

公开(公告)号：US20250166721A1

公开(公告)日：2025-05-22

申请号：US18761985

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha PARK ,  Seaeun Park ,  Saeeun Kim

IPC: G11C29/32 ,  G06F11/22

Abstract: A nonvolatile memory device includes at least one first universal interface bus (UIB) circuit coupled to a plurality of input/output (I/O) pads, at least one second UIB circuit coupled to the plurality of I/O pads, a core block including a first input terminal coupled to another block, and a plurality of second input terminals coupled to a first output terminal of the at least one first UIB circuit and a second output terminal of the at least one second UIB circuit, and at least one block configured to activate the at least one second UIB circuit.

公开(公告)号：US20250027992A1

公开(公告)日：2025-01-23

申请号：US18671560

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seaeun Park ,  Saeeun Kim ,  Thai Hoang Nguyen ,  Joon-sung Yang

IPC: G01R31/3185

Abstract: An integrated circuit may include a plurality of combinational logic circuits including a first combinational logic circuit, a plurality of flip-flops including a first flip-flop configured to receive a first scan input signal and a first data signal, and a first core block including a multiplexer. The multiplexer may be configured to select, based on a test control signal, one of a primary input signal received through a primary input terminal and an output signal of the first flip-flop and provide the selected signal to the first combinational logic circuit. The first flip-flop may be further configured to selectively receive, based on a scan control signal, one of the first scan input signal and the first data signal.

公开(公告)号：US20240210471A1

公开(公告)日：2024-06-27

申请号：US18338471

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seaeun Park

IPC: G01R31/3185 ,  G06F30/333

CPC classification number: G01R31/318547 ,  G01R31/318591 ,  G06F30/333

Abstract: Disclosed is a method of testing an electronic device, which includes receiving, by a computer, a circuit layout, generating, by the computer, a design for test (DFT) layout from the circuit layout, generating, by the computer, a test pattern by using an electronic design automation (EDA) tool, based on the DFT layout, and generating, by the computer, a hybrid layout from the DFT layout, and the electronic device manufactured by using the hybrid layout is tested by using the test pattern.

公开(公告)号：US11906584B2

公开(公告)日：2024-02-20

申请号：US17838298

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seaeun Park

IPC: G01R31/3183 ,  G06F30/31 ,  G06F119/02

CPC classification number: G01R31/318357 ,  G06F30/31 ,  G06F2119/02

Abstract: A simulation method and system of verifying an operation of a semiconductor memory device of a memory module at a design level. The simulation method includes setting a configuration and an arrangement of a registered clock driver (RCD) and a configuration and an arrangement of first semiconductor memory devices to fourth semiconductor memory devices, on a printed circuit board (PCB) through a graphic user interface (GUI). When a RCD test execution command is applied through the GUI, executing a test program to apply control signals to control signal terminals of the PCB based on a command truth table, to compare the applied control signals and control signals output through first driver output terminals of the RCD, and to create an RCD test result. When the RCD operates normally, performing a test on the memory module.