公开(公告)号：US20180158829A1

公开(公告)日：2018-06-07

申请号：US15712479

申请日：2017-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hoon SONG ,  Kiheum NAM ,  Wonchul LEE

IPC: H01L27/108 ,  H01L27/02 ,  H01L21/768 ,  H01L23/528 ,  H01L29/41

CPC classification number: H01L27/10844 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/90 ,  H01L29/41

Abstract: A semiconductor device includes a plurality of pillar structures on a semiconductor substrate, and a support pattern in contact with at least a part of each of the pillar structures, the support pattern connecting the pillar structures with one another, wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including at least a first support hole and a second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other.

公开(公告)号：US20240179890A1

公开(公告)日：2024-05-30

申请号：US18374870

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byunghoon CHO ,  Namjung KANG ,  Kiheum NAM ,  Jihyun CHOI

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor device includes a peripheral circuit transistor disposed in a peripheral circuit region. First connection lines and second connection lines are disposed on a same plane above the peripheral circuit transistor. The second connection lines including a cutting portion. A cell capacitor is disposed on the substrate in a cell region. A first plate pattern is on the cell capacitor. A second plate pattern is on a portion of a surface of the first plate pattern. A first contact plug directly contacts an upper surface of the second plate pattern. A third connection line is disposed above the second connection line. The third connection line faces the cutting portion. Second contact plugs extend vertically to directly contact both sidewalls of the third connection line and upper surfaces of the second connection lines. The third connection line is disposed on a same plane as the second plate pattern.

公开(公告)号：US20190296022A1

公开(公告)日：2019-09-26

申请号：US16440399

申请日：2019-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hoon SONG ,  Kiheum NAM ,  Wonchul LEE

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/528 ,  H01L29/41 ,  H01L49/02

Abstract: A semiconductor device includes a plurality of pillar structures on a semiconductor substrate, and a support pattern in contact with at least a part of each of the pillar structures, the support pattern connecting the pillar structures with one another, wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including at least a first support hole and a second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other.