MEMORY CONTROLLER MANAGING READ LEVEL INFORMATION, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY CONTROLLER

    公开(公告)号:US20250165339A1

    公开(公告)日:2025-05-22

    申请号:US18753410

    申请日:2024-06-25

    Abstract: An operating method of a memory controller is provided. The method includes: in a first super block including first blocks of memory chips, storing a first read level with respect to a first block in a first memory as first super block read level (RL) information; storing the first read level in a second memory as first chip RL information corresponding to the first memory chip; during the read operation on the first blocks included in the first super block, controlling the read operation based on the first super block RL information stored in the first memory; and based on a failure occurring in data read from the first block of the first memory chip by using the first super block RL information, controlling the read operation on the first block of the first memory chip based on the first chip RL information stored in the second memory.

    MEMORY DEVICES
    2.
    发明公开
    MEMORY DEVICES 审中-公开

    公开(公告)号:US20240188305A1

    公开(公告)日:2024-06-06

    申请号:US18526031

    申请日:2023-12-01

    CPC classification number: H10B63/22 H10B63/10 H10B63/80

    Abstract: A memory device includes a substrate; a plurality of first conductive lines on the substrate and extending in a first direction; a plurality of second conductive lines on the plurality of first conductive lines and extending in a second direction crossing the first direction; and a plurality of first memory cells respectively arranged between the plurality of first conductive lines and the plurality of second conductive lines, wherein each first memory cell of the plurality of first memory cells includes a switching device and a variable resistance material pattern, and the switching device includes a material having a composition of LaxNi1-xOy, in which 0.13≤x≤0.30 and 0.9≤y≤1.5.

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