公开(公告)号：US11653490B2

公开(公告)日：2023-05-16

申请号：US17471778

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokho Shin ,  Taegyu Kang ,  Byeungmoo Kang ,  Joongchan Shin

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

Abstract: A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

公开(公告)号：US12156401B2

公开(公告)日：2024-11-26

申请号：US17477634

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Byeungmoo Kang ,  Sangyeon Han

IPC: H10B41/27 ,  G11C5/06 ,  H01L23/538 ,  H10B43/27

Abstract: A three-dimensional (3D) semiconductor memory device including: stack structures spaced apart from each other on a semiconductor substrate, wherein each of the stack structures includes interlayer insulating layers and semiconductor patterns alternately stacked on the semiconductor substrate; conductive patterns provided between the interlayer insulating layers vertically adjacent to each other and connected to the semiconductor patterns; and a protective structure covering a top surface of the semiconductor substrate between the stack structures, wherein a top surface of the protective structure is located between a top surface and a bottom surface of a lowermost interlayer insulating layer of the interlayer insulating layers.

公开(公告)号：US20220093626A1

公开(公告)日：2022-03-24

申请号：US17477634

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Byeungmoo Kang ,  Sangyeon Han

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/538

Abstract: A three-dimensional (3D) semiconductor memory device including: stack structures spaced apart from each other on a semiconductor substrate, wherein each of the stack structures includes interlayer insulating layers and semiconductor patterns alternately stacked on the semiconductor substrate; conductive patterns provided between the interlayer insulating layers vertically adjacent to each other and connected to the semiconductor patterns; and a protective structure covering a top surface of the semiconductor substrate between the stack structures, wherein a top surface of the protective structure is located between a top surface and a bottom surface of a lowermost interlayer insulating layer of the interlayer insulating layers.