公开(公告)号：US10019380B2

公开(公告)日：2018-07-10

申请号：US14866228

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GadelRab ,  Jason Edward Podaima ,  Ruolong Liu ,  Alexander Miretsky ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Simon Peter William Booth ,  Meghal Varia ,  Thomas David Dryburgh

IPC: G06F12/00 ,  G06F12/1072 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/1072 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.

公开(公告)号：US20170091116A1

公开(公告)日：2017-03-30

申请号：US14866228

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GadelRab ,  Jason Edward Podaima ,  Ruolong Liu ,  Alexander Miretsky ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Simon Peter William Booth ,  Meghal Varia ,  Thomas David Dryburgh

IPC: G06F12/10

CPC classification number: G06F12/1072 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.