公开(公告)号：US09697320B2

公开(公告)日：2017-07-04

申请号：US14864156

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Sreedhar Gudala ,  Kumar Gopal Rao ,  Francis Page ,  Pak Kin Wong ,  Sunil Kumar

IPC: G06F17/50 ,  G06F15/78 ,  G06F11/14 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F17/5072 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1423 ,  G06F12/0646 ,  G06F15/7807 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2212/2542 ,  G06F2213/0038 ,  G06F2217/66

Abstract: Circuits and methods for a system on a chip having non-uniform channel spacings is provided. In an example, a chip is provided that includes a first functional block having a rectilinear shape, the first processing unit having on a side a plurality of channel spacings. A first channel spacing of the plurality of channel spacings is positioned in contact with the side and a second functional block. A second channel spacing of the plurality of channel spacings is positioned in contact with the side and the second functional block. The width of the second channel spacing is non-uniform with the width of the first channel spacing.

公开(公告)号：US20150200667A1

公开(公告)日：2015-07-16

申请号：US14155734

申请日：2014-01-15

Applicant: QUALCOMM Incorporated

Inventor： Shiva Ram Chandrasekaran ,  Chandrasekhar Reddy Singasani ,  Joey Dacanay ,  Mamta Bansal ,  Arman Ohanian ,  Satish Raj ,  Kiran Srinivasa Sastry ,  Abhirami Senthilkumaran ,  Tarek Zghal ,  Parissa Najdesamii ,  Sunil Kumar

IPC: H03K19/00 ,  G06F1/32

CPC classification number: H03K19/0008 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

Abstract: Provided are systems and methods for reducing power consumption in the interface and routing circuitry associated with various core modules of an integrated circuit or system. One system includes core modules, glue logic domains adapted to interface the plurality of core modules, and a power controller electrically coupled to the glue logic domains. Each glue logic domain includes a glue logic module implemented as a soft macro with metal traces extending beyond an extent of the glue logic module. The power controller decouples power from selected glue logic domains based on control signals and/or detected power down states of core modules and/or other glue logic domains. The power controller facilitates the power transitions using logic state retention, logic state clamping, ordered or scheduled transitioning, and/or other power transition systems and methods.

Abstract translation: 提供了用于降低与集成电路或系统的各种核心模块相关联的接口和路由电路中的功耗的系统和方法。 一个系统包括核心模块，适于接合多个核心模块的胶合逻辑域，以及电连接到胶合逻辑域的功率控制器。 每个胶合逻辑域包括实现为具有超出胶合逻辑模块的范围的金属迹线的软宏的胶合逻辑模块。 功率控制器基于核心模块和/或其他胶合逻辑域的控制信号和/或检测到的掉电状态来将电力与选定的胶合逻辑域分离。 功率控制器使用逻辑状态保持，逻辑状态钳位，有序或调度转换和/或其他功率转换系统和方法来促进功率转换。

公开(公告)号：US20170091365A1

公开(公告)日：2017-03-30

申请号：US14864156

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Sreedhar Gudala ,  Kumar Gopal Rao ,  Francis Page ,  Pak Kin Wong ,  Sunil Kumar

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1423 ,  G06F12/0646 ,  G06F15/7807 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2212/2542 ,  G06F2213/0038 ,  G06F2217/66

Abstract: Circuits and methods for a system on a chip having non-uniform channel spacings is provided. In an example, a chip is provided that includes a first functional block having a rectilinear shape, the first processing unit having on a side a plurality of channel spacings. A first channel spacing of the plurality of channel spacings is positioned in contact with the side and a second functional block. A second channel spacing of the plurality of channel spacings is positioned in contact with the side and the second functional block. The width of the second channel spacing is non-uniform with the width of the first channel spacing.