公开(公告)号：US10319425B1

公开(公告)日：2019-06-11

申请号：US15939514

申请日：2018-03-29

Applicant: QUALCOMM Incorporated ,  Yonsei University, University-Industry Foundation

Inventor： Seong-Ook Jung ,  Byungkyu Song ,  Sungryul Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16

Abstract: Offset-cancellation sensing circuit (OCSC)-based Non-volatile (NV) memory circuits are disclosed. An OCSC-based NV memory circuit includes a latch circuit configured to latch a memory state from an input signal. The OCSC-based NV memory circuit also includes a sensing circuit that includes NV memory devices configured to store the latched memory state in the latch circuit for restoring the memory state in the latch circuit when recovering from a reduced power level in an idle mode. To avoid the need to increase transistor size in the sensing circuit to mitigate restoration degradation, the sensing circuit is also configured to cancel an offset voltage of a differential amplifier in the sensing circuit. In other exemplary aspects, the NV memory devices are included in the sensing circuit and coupled to the differential transistors as NMOS transistors in the differential amplifier, eliminating contribution of offset voltage from other differential PMOS transistors not included.

公开(公告)号：US09691462B2

公开(公告)日：2017-06-27

申请号：US14499153

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Taehui Na ,  Byungkyu Song ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C2207/002

Abstract: Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.