公开(公告)号：US20240370575A1

公开(公告)日：2024-11-07

申请号：US18691811

申请日：2022-08-03

Applicant: QUALCOMM Incorporated

Inventor： Marcel SELHORST ,  Alexander DENT ,  Joona Verneri KANNISTO ,  Akash VERMA

IPC: G06F21/57

Abstract: Various embodiments include methods and devices for circumventing processor error induced vulnerability. Embodiments may include determining whether a condition indicative of an error in a processor exists for a first processor, and preventing use of the first processor in response to determining that the condition indicative of the error in the processor exists for the first processor. In some embodiments, preventing use of the first processor may include transitioning the first processor to a low power state. In some embodiments, preventing use of the first processor may include preventing the first processor from being registered with an operating system. In some embodiments, the condition indicative of the error in the processor may include an enabled non-secure debug feature of the processor and a disabled secure debug feature of the processor.