公开(公告)号：US10713189B2

公开(公告)日：2020-07-14

申请号：US15634701

申请日：2017-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： Vasantha Kumar Bandur Puttappa ,  Umesh Rao ,  Kunal Desai

IPC: G06F11/30 ,  G06F13/16 ,  H04B1/3827 ,  G06F15/78 ,  G06F5/06 ,  G06F1/32

Abstract: Methods and systems for dynamically controlling buffer size in a computing device in a computing device (“PCD”) are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a first buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

公开(公告)号：US20180373652A1

公开(公告)日：2018-12-27

申请号：US15634701

申请日：2017-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： Vasantha Kumar Bandur Puttappa ,  Umesh Rao ,  Kunal Desai

IPC: G06F13/16 ,  H04B1/3827 ,  G06F15/78 ,  G06F11/30

Abstract: Methods and systems for dynamically controlling buffer size in a computing device in a computing device (“PCD”) are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a fist buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

公开(公告)号：US20170083461A1

公开(公告)日：2017-03-23

申请号：US14861114

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Kunal Desai ,  Aniket Aphale ,  Umesh Rao

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1615 ,  G06F13/1689 ,  G06F13/4068

Abstract: An integrated circuit is provided with a memory controller coupled to a buffered command and address bus and a pipelined data bus having a pipeline delay. The memory controller is configured to control the write and read operations for an external memory having a write latency period requirement. The memory controller is further configured to launch write data into the pipelined data bus responsive to the expiration of a modified write latency period that is shorter than the write latency period.