公开(公告)号：US20200285584A1

公开(公告)日：2020-09-10

申请号：US16292178

申请日：2019-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Raghavendra Srinivas ,  Kaustav Roychowdhury ,  Siddesh Halavarthi Math Revana ,  Srivatsa Vaddagiri ,  Satyaki Mukherjee

IPC: G06F12/0891 ,  G06F12/0837 ,  G06F12/0842 ,  G06F12/0897

Abstract: Aborting a cache memory flush may include initiating a flush operation in which a plurality of cache lines are flushed from a cache memory associated with a processor core that is entering a power collapse mode. Assertion of a wake-up signal associated with the processor core entering the power collapse mode may be detected. The wake-up signal may occur before completion of the flush operation. The flush operation may cease or abort in response to detecting the wake-up signal.