公开(公告)号：US20170277461A1

公开(公告)日：2017-09-28

申请号：US15081915

申请日：2016-03-27

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  DEXTER TAMIO CHUN ,  ALAIN ARTIERE

IPC: G06F3/06 ,  G11C11/406 ,  G06F12/08

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/602 ,  G11C11/40607 ,  Y02D10/13

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem adjusts access to the DRAM based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.