公开(公告)号：US11974071B2

公开(公告)日：2024-04-30

申请号：US17892117

申请日：2022-08-21

Applicant: MEDIATEK INC.

Inventor： Kang-Yi Fan ,  Chin-Wen Liang ,  Chang-Chu Liu ,  Sheng-Hsiang Chang ,  You-Min Yeh

IPC: H04N7/01

CPC classification number: H04N7/013

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

公开(公告)号：US20220408054A1

公开(公告)日：2022-12-22

申请号：US17892117

申请日：2022-08-21

Applicant: MEDIATEK INC.

Inventor： Kang-Yi Fan ,  Chin-Wen Liang ,  Chang-Chu Liu ,  Sheng-Hsiang Chang ,  You-Min Yeh

IPC: H04N7/01

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

公开(公告)号：US11457173B2

公开(公告)日：2022-09-27

申请号：US17153892

申请日：2021-01-21

Applicant: MEDIATEK INC.

Inventor： Kang-Yi Fan ,  Chin-Wen Liang ,  Chang-Chu Liu ,  Sheng-Hsiang Chang ,  You-Min Yeh

IPC: H04N7/01

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

公开(公告)号：US20210280148A1

公开(公告)日：2021-09-09

申请号：US17183380

申请日：2021-02-24

Applicant: MEDIATEK INC.

Inventor： Chang-Chu Liu ,  Sheng-Hsiang Chang ,  Kang-Yi Fan ,  You-Min Yeh

IPC: G09G5/00

Abstract: The present invention provides a processor including a source generator, a request synchronization signal generator and an output circuit. The source generator is configured to generate image data of a frame. The request synchronization signal generator is configured to generate a request synchronization signal to an integrated circuit only after the source generator generates the image data of the frame completely, wherein the request synchronization signal is used to trigger the integrated circuit to send a synchronization signal to the processor. The output circuit is configured to send the image data of the frame to the integrated circuit only after receiving the synchronization signal generated from the integrated circuit in response to the request synchronization signal.

公开(公告)号：US20210266495A1

公开(公告)日：2021-08-26

申请号：US17153892

申请日：2021-01-21

Applicant: MEDIATEK INC.

Inventor： Kang-Yi Fan ,  Chin-Wen Liang ,  Chang-Chu Liu ,  Sheng-Hsiang Chang ,  You-Min Yeh

IPC: H04N7/01

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

公开(公告)号：US20170287106A1

公开(公告)日：2017-10-05

申请号：US15630252

申请日：2017-06-22

Applicant: MediaTek Inc.

Inventor： Chang-Chu Liu ,  Jun-Jie Jiang ,  Chiung-Fu Chen ,  You-Min Yeh

IPC: G06T1/60 ,  G06T1/20 ,  G06T11/60

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T11/00 ,  G06T11/60 ,  G06T2210/62

Abstract: A device generates blended frames, with each blended frame composed of multiple image layers and each image layer composed of multiple regions. The device includes display hardware. The display hardware retrieves a given image layer in a current frame from a memory. Based on at least content hints generated at the display hardware for the given image layer in the current frame, the display hardware makes a determination of whether to skip access to the memory for retrieving each region of each image layer in a next frame that is immediately after the current frame, and accesses the memory for the next frame according to the determination.