Abstract:
A packet buffer stores packet data of packets received by a master device. The packet buffer includes a non-guaranteed buffer, a guaranteed buffer, and a reserved buffer. The non-guaranteed buffer is visible to the master device, and is not guaranteed to provide one free cell space for one cell in a first-type packet before the non-guaranteed buffer is full. The guaranteed buffer is visible to the master device, and is guaranteed to provide one free cell space for one cell in a second-type packet before the guaranteed buffer is full. The reserved buffer is invisible to the master device, and is arranged to provide headroom for the guaranteed buffer.
Abstract:
A random early drop (RED) based processing circuit includes a scheduler, an RED-based decision logic and a controller. The scheduler generates a trigger event according to an RED-based operation schedule. The scheduler is coupled to a software interface, and the RED-based operation schedule in the scheduler is programmed via the software interface. The RED-based decision logic performs at least a first RED-based operation to generate a first RED decision accordingly. The controller receives at least the trigger event, and triggers the RED-based decision logic to perform the first RED-based operation according to at least the trigger event.