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1.发明申请DECODING METHOD AND DECODING APPARATUS FOR USING PARALLEL PROCESSING SCHEME TO DECODE PICTURES IN DIFFERENT BITSTREAMS AFTER REQUIRED DECODED DATA DERIVED FROM DECODING PRECEDING PICTURE(S) IS READY 有权使用并行处理方案的解码方法和解码设备在需要从解码图像中提取的解码数据之后，在不同的数据库中解码图像准备就绪公开(公告)号：US20140022344A1
公开(公告)日：2014-01-23
申请号：US14035962
申请日：2013-09-25
Applicant: MEDIATEK INC.
Inventor： Te-Chi Hsiao , Yung-Chang Chang , Ching-Chieh Wang , Shih-Hung Lin , Chi-Cheng Ju
IPC: H04N13/00
CPC classification number: H04N13/161 , H04N19/30 , H04N19/44 , H04N19/597 , H04N21/234327
Abstract: An exemplary decoding method of an input video bitstream including a first bitstream and a second bitstream includes: decoding a first picture in the first bitstream; after a required decoded data derived from decoding the first picture is ready for a first decoding operation of a second picture in the first bitstream, performing the first decoding operation; and after a required decoded data derived from decoding the first picture is ready for a second decoding operation of a picture in the second bitstream, performing the second decoding operation, wherein a time period of decoding the second picture in the first bitstream and a time period of decoding the picture in the second bitstream are overlapped in time.
Abstract translation: 包括第一比特流和第二比特流的输入视频比特流的示例性解码方法包括：对第一比特流中的第一图像进行解码; 在从第一图像解码得到的所需解码数据准备好进行第一比特流中的第二图像的第一解码操作之后，执行第一解码操作; 并且在从第一图像的解码得到的所需解码数据准备好进行第二比特流中的图像的第二解码操作之后，执行第二解码操作，其中对第一比特流中的第二图像进行解码的时间段和时间段 对第二位流中的图像进行解码的时间重叠。
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公开(公告)号：US20130264681A1
公开(公告)日：2013-10-10
申请号：US13907981
申请日：2013-06-03
Applicant: MEDIATEK INC.
Inventor： Chao-Chun Tu , Shih-Hung Lin , Chih-Chien Huang , Tien-Chang Chang
IPC: H01L23/538
CPC classification number: H01L23/00 , H01L21/00 , H01L23/5223 , H01L23/5286 , H01L23/5384 , H01L27/00 , H01L28/00 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.
Abstract translation: 集成电路芯片包括半导体衬底; 第一互连线，其具有在所述半导体衬底上的第一部分和第二部分，其中所述第二部分与所述第一部分分离; 位于所述第一互连线下方的第二互连线; 第一导电通孔，电连接第一部分与第二互连线; 位于第一互连线和第二互连线之间的导电层; 以及将导电层与第二部分电耦合的第二导电通孔。
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3.发明授权Decoding method and decoding apparatus for using parallel processing scheme to decode pictures in different bitstreams after required decoded data derived from decoding preceding picture(s) is ready 有权解码方法和解码装置，用于使用并行处理方案在从解码先前图像导出的所需解码数据之后对不同位流中的图像进行解码公开(公告)号：US09565418B2
公开(公告)日：2017-02-07
申请号：US14035962
申请日：2013-09-25
Applicant: MEDIATEK INC.
Inventor： Te-Chi Hsiao , Yung-Chang Chang , Ching-Chieh Wang , Shih-Hung Lin , Chi-Cheng Ju
IPC: H04N7/18 , H04N13/00 , H04N21/2343 , H04N19/597 , H04N19/44 , H04N19/30
CPC classification number: H04N13/161 , H04N19/30 , H04N19/44 , H04N19/597 , H04N21/234327
Abstract: An exemplary decoding method of an input video bitstream including a first bitstream and a second bitstream includes: decoding a first picture in the first bitstream; after a required decoded data derived from decoding the first picture is ready for a first decoding operation of a second picture in the first bitstream, performing the first decoding operation; and after a required decoded data derived from decoding the first picture is ready for a second decoding operation of a picture in the second bitstream, performing the second decoding operation, wherein a time period of decoding the second picture in the first bitstream and a time period of decoding the picture in the second bitstream are overlapped in time.
Abstract translation: 包括第一比特流和第二比特流的输入视频比特流的示例性解码方法包括：对第一比特流中的第一图像进行解码; 在从第一图像解码得到的所需解码数据准备好进行第一比特流中的第二图像的第一解码操作之后，执行第一解码操作; 并且在从第一图像的解码得到的所需解码数据准备好进行第二比特流中的图像的第二解码操作之后，执行第二解码操作，其中对第一比特流中的第二图像进行解码的时间段和时间段 对第二位流中的图像进行解码的时间重叠。
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公开(公告)号：US08766417B2
公开(公告)日：2014-07-01
申请号：US13907981
申请日：2013-06-03
Applicant: Mediatek Inc.
Inventor： Chao-Chun Tu , Shih-Hung Lin , Chih-Chien Huang , Tien-Chang Chang
IPC: H01L23/495 , H01L23/00 , H01L49/02 , H01L27/00 , H01L21/00
CPC classification number: H01L23/00 , H01L21/00 , H01L23/5223 , H01L23/5286 , H01L23/5384 , H01L27/00 , H01L28/00 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.
Abstract translation: 集成电路芯片包括半导体衬底; 第一互连线，其具有在所述半导体衬底上的第一部分和第二部分，其中所述第二部分与所述第一部分分离; 位于所述第一互连线下方的第二互连线; 第一导电通孔，电连接第一部分与第二互连线; 位于第一互连线和第二互连线之间的导电层; 以及将导电层与第二部分电耦合的第二导电通孔。
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