Smart Frequency Boost For Graphics-Processing Hardware
    1.
    发明申请
    Smart Frequency Boost For Graphics-Processing Hardware 审中-公开
    用于图形处理硬件的智能频率提升

    公开(公告)号:US20160055615A1

    公开(公告)日:2016-02-25

    申请号:US14932486

    申请日:2015-11-04

    Applicant: MediaTek Inc.

    Inventor: Po-hua Huang

    CPC classification number: G06T1/20 G06F1/324 G06F1/3296 Y02D10/126 Y02D10/172

    Abstract: A technique, as well as select implementations thereof, pertaining to smart frequency boost for graphics-processing hardware is described. A method may involve monitoring a queue of a plurality of graphics-related processes pending to be executed by a graphics-processing hardware to determine whether one or more predetermined conditions of the graphics-related processes in the queue are met. The one or more predetermined conditions may include an accumulation condition of the graphics-related processes in the queue. The method may also involve dynamically adjusting at least one operating parameter of the graphics-processing hardware in response to a determination that each of the one or more predetermined conditions of the graphics-related processes in the queue is met.

    Abstract translation: 描述了涉及用于图形处理硬件的智能频率提升的技术及其选择实现。 一种方法可以包括监视多个与图形处理硬件执行的图形相关进程的队列,以确定是否满足队列中图形相关进程的一个或多个预定条件。 一个或多个预定条件可以包括队列中图形相关进程的累积条件。 该方法还可以涉及响应于满足队列中的图形相关进程的一个或多个预定条件中的每一个的确定来动态地调整图形处理硬件的至少一个操作参数。

    Deep learning model inference for dynamic input shapes

    公开(公告)号:US12223300B2

    公开(公告)日:2025-02-11

    申请号:US18309341

    申请日:2023-04-28

    Applicant: MEDIATEK INC.

    Abstract: A method of compiling a deep learning model includes reading metadata from a compiled result, the metadata indicating a structure of the deep learning model corresponding to a low-level IR, receiving shape information of an input tensor of the deep learning model, determining a shape of an output tensor of a first computation operation of the computation operations based on the shape information of the input tensor of the deep learning model and the structure of the deep learning model, tiling the output tensor of the first computation operation into one or more tiles according to the shape of the output tensor of the first computation operation and hardware limitations of a processor executing the deep learning model, and patching one or more copies of a templated hardware command into executable hardware commands.

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