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1.发明授权Decoding apparatus with de-interleaving efforts distributed to different decoding phases and related decoding method thereof 有权具有解交织功能的解码装置分配到不同的解码阶段及其相关的解码方法公开(公告)号：US09015551B2
公开(公告)日：2015-04-21
申请号：US13798112
申请日：2013-03-13
Applicant: MediaTek Inc.
Inventor： Wei-De Wu , Chiaming Lo
CPC classification number: H03M13/2778 , H03M13/271 , H03M13/2714 , H03M13/2775 , H03M13/2957 , H03M13/3905 , H03M13/3972
Abstract: A decoding apparatus includes a memory device and a decoding circuit. The memory device is arranged for storing a data block with inter-row interleaving in a plurality of data rows of the data block and without intra-row interleaving in each of the data rows. The decoding circuit is coupled to the memory device. The decoding circuit is arranged for accessing the memory device to perform a first decoding operation with inter-row de-interleaving memory access, and accessing the memory device to perform a second decoding operation with intra-row de-interleaving memory access.
Abstract translation: 解码装置包括存储装置和解码电路。 存储器件被布置为在数据块的多个数据行中存储具有行间交错的数据块，并且在每个数据行中不存在行内交织。 解码电路耦合到存储器件。 解码电路被布置为访问存储器件以执行具有行间解交织存储器访问的第一解码操作，并且访问存储器件以执行具有行内解交织存储器访问的第二解码操作。
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2.发明申请公开(公告)号：US20130283120A1
公开(公告)日：2013-10-24
申请号：US13798112
申请日：2013-03-13
Applicant: MEDIATEK INC.
Inventor： Wei-De Wu , Chiaming Lo
IPC: H03M13/27
CPC classification number: H03M13/2778 , H03M13/271 , H03M13/2714 , H03M13/2775 , H03M13/2957 , H03M13/3905 , H03M13/3972
Abstract: A decoding apparatus includes a memory device and a decoding circuit. The memory device is arranged for storing a data block with inter-row interleaving in a plurality of data rows of the data block and without intra-row interleaving in each of the data rows. The decoding circuit is coupled to the memory device. The decoding circuit is arranged for accessing the memory device to perform a first decoding operation with inter-row de-interleaving memory access, and accessing the memory device to perform a second decoding operation with intra-row de-interleaving memory access memory access.
Abstract translation: 解码装置包括存储装置和解码电路。 存储器件被布置为在数据块的多个数据行中存储具有行间交错的数据块，并且在每个数据行中不存在行内交织。 解码电路耦合到存储器件。 解码电路被布置为访问存储器件以执行具有行间解交织存储器访问的第一解码操作，并且访问存储器件以执行具有行内去交织存储器访问存储器访问的第二解码操作。
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