公开(公告)号：US20040057506A1

公开(公告)日：2004-03-25

申请号：US10686057

申请日：2003-10-14

Applicant: InterDigital Technology Corporation

Inventor： Aykut Bultan ,  Donald Grieco

IPC: H04B001/707

CPC classification number: H04B1/7085 ,  H04B1/709 ,  H04L7/0029

Abstract: The present invention is for a receiver incorporated into User Equipment (UE) or base stations of a code division multiple access (CDMA) communication system. The UE and base station are in communication with one of the plurality of base stations and receives a communication signal through the receiver. The communication signal is correlated using a delay locked code tracking loop, that estimates and tracks a channel delay. The tracking loop comprises a reference code generator and an interpolator for generating timed signal versions in response to said communication. A timed signal correlator, included in the tracking loop for correlating at least two of the timed signal versions with the code reference signal. The result of the correlation is used for generating an error signal. An automatic power normalization loop (APN), that is responsive to the interpolator, generates a power error signal that normalizes the error signal through a normalization circuit.

Abstract translation: 本发明涉及一种并入用户设备（UE）或码分多址（CDMA）通信系统的基站的接收机。 UE和基站与多个基站之一进行通信，并通过接收机接收通信信号。 使用延迟锁定码跟踪环路对通信信号进行相关，该循环估计和跟踪信道延迟。 跟踪环路包括参考码发生器和用于响应于所述通信产生定时信号版本的内插器。 定时信号相关器，包括在用于将至少两个定时信号版本与代码参考信号相关联的跟踪环路中。 相关的结果用于产生误差信号。 响应于内插器的自动功率归一化回路（APN）产生通过归一化电路对误差信号进行归一化的功率误差信号。

公开(公告)号：US20030063657A1

公开(公告)日：2003-04-03

申请号：US10252640

申请日：2002-09-23

Applicant: InterDigital Technology Corporation

Inventor： Aykut Bultan ,  Donald M. Grieco

IPC: H04B001/69

CPC classification number: H04B1/7085 ,  H04B1/709 ,  H04L7/0029

Abstract: The present invention is for a receiver incorporated into User Equipment (UE) or base stations of a code division multiple access (CDMA) communication system. The UE and base station are in communication with one of the plurality of base stations and receives a communication signal through the receiver. The communication signal is correlated using a delay locked code tracking loop, that estimates and tracks a channel delay. The tracking loop comprises a reference code generator and an interpolator for generating timed signal versions in response to said communication. A timed signal correlator, included in the tracking loop for correlating at least two of the timed signal versions with the code reference signal. The result of the correlation is used for generating an error signal. An automatic power normalization loop (APN), that is responsive to the interpolator, generates a power error signal that normalizes the error signal through a normalization circuit.

公开(公告)号：US20040120387A1

公开(公告)日：2004-06-24

申请号：US10676152

申请日：2003-09-29

Applicant: InterDigital Technology Corporation

Inventor： Aykut Bultan ,  Donald M. Grieco

IPC: H04B001/707

CPC classification number: H04L7/0029 ,  H04B1/70756 ,  H04B1/7077 ,  H04B1/7117 ,  H04L7/0004 ,  H04L25/0202

Abstract: A digital timing synchronizer of a receiver is provided for timing synchronization to a transmitter in a wireless communication system, wherein the received signal has a timing error with respect to a reference code. A channel estimator estimates an initial code phase of the received signal. A code generator generates a timing reference code that is adjustable by integer increments. An interpolation feedback circuit is configured for interpolation and correction of the timing error, whereby the interpolation is achieved through an integer code shift, plus a quantized fractional adjustment selected from a look-up table of quantized fractional adjustment values and their associated predetermined interpolator coefficients, from which a time corrected version of the received signal is produced.

Abstract translation: 接收机的数字定时同步器被提供用于在无线通信系统中与发射机进行定时同步，其中所接收的信号相对于参考码具有定时误差。 信道估计器估计接收信号的初始码相位。 代码生成器生成可以整数增量调整的定时参考代码。 内插反馈电路被配置为用于定时误差的内插和校正，由此通过整数代码移位加上从量化分数调整值的查找表及其相关联的预定内插器系数中选择的量化分数调整来实现内插， 由此产生接收信号的时间校正版本。