公开(公告)号：US20140344522A1

公开(公告)日：2014-11-20

申请号：US14328173

申请日：2014-07-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lingjun Fan ,  Shibin Tang ,  Da Wang ,  Hao Zhang ,  Dongrui Fan

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F1/3275 ,  G06F12/0833 ,  G06F12/0891 ,  G06F12/0895 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/621 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/13 ,  Y02D10/14

Abstract: The present invention provides a dynamic set associative cache apparatus for a processor. When read access occurs, the apparatus first determines a valid/invalid bit of each cache block in a cache set to be accessed, and sets, according to the valid/invalid bit of each cache block, an enable/disable bit of a cache way in which the cache block is located; then, reads valid cache blocks, compares a tag section in a memory address with a tag block in each cache block that is read, and if there is a hit, reads data from a data block in a hit cache block according to an offset section of the memory address.

Abstract translation: 本发明提供了一种用于处理器的动态组关联高速缓存装置。 当读取访问发生时，设备首先确定要访问的高速缓存集中的每个高速缓存块的有效/无效位，并根据每个高速缓存块的有效/无效位设置缓存方式的使能/禁止位 其中高速缓存块位于其中; 然后，读取有效的高速缓存块，将存储器地址中的标签部分与读取的每个高速缓存块中的标签块进行比较，并且如果存在命中，则根据偏移部分从命中高速缓存块中的数据块读取数据 的内存地址。

公开(公告)号：US09880937B2

公开(公告)日：2018-01-30

申请号：US14328173

申请日：2014-07-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lingjun Fan ,  Shibin Tang ,  Da Wang ,  Hao Zhang ,  Dongrui Fan

IPC: G06F12/08 ,  G06F1/32 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/0831 ,  G06F12/0891

CPC classification number: G06F12/0864 ,  G06F1/3275 ,  G06F12/0833 ,  G06F12/0891 ,  G06F12/0895 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/621 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/13 ,  Y02D10/14

Abstract: The present invention provides a dynamic set associative cache apparatus for a processor. When read access occurs, the apparatus first determines a valid/invalid bit of each cache block in a cache set to be accessed, and sets, according to the valid/invalid bit of each cache block, an enable/disable bit of a cache way in which the cache block is located; then, reads valid cache blocks, compares a tag section in a memory address with a tag block in each cache block that is read, and if there is a hit, reads data from a data block in a hit cache block according to an offset section of the memory address.