公开(公告)号：US20230367913A1

公开(公告)日：2023-11-16

申请号：US18356463

申请日：2023-07-21

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Jianwei JIA ,  Feifei YIN ,  Gang FENG ,  Yu LIU

IPC: G06F21/64 ,  G06F21/57

CPC classification number: G06F21/64 ,  G06F21/575 ,  G06F2221/034

Abstract: The present disclosure relates to a terminal chip and a measurement method thereof. In an example, a terminal chip includes a computing subsystem and a security subsystem. The security subsystem is configured to measure the computing subsystem. A boot time of the security subsystem is earlier than a boot time of the computing subsystem. The security subsystem includes an integrity verification unit configured to perform integrity measurement on data in a boot process of the computing subsystem.

公开(公告)号：US20190266360A1

公开(公告)日：2019-08-29

申请号：US16412932

申请日：2019-05-15

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Feifei YIN ,  Yu LIU ,  Jiayin LU

IPC: G06F21/75 ,  G06F21/72 ,  G06F21/60

Abstract: The present application provides example terminal chips. One example terminal chip includes a security element, an application processor, and an interface module configured to transfer information between the application processor and the security element. The terminal chip includes a first power interface configured to receive power outside the terminal chip. A first power input port of the security element is connected to the first power interface, and at least one of the application processor or the interface module is connected to the first power interface. In the example terminal chip, a power supply port of the security element is connected to a power supply port of the application processor or the interface module of the terminal chip.

公开(公告)号：US20180137311A1

公开(公告)日：2018-05-17

申请号：US15814091

申请日：2017-11-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tao LIU ,  Yu LIU ,  Feifei YIN

IPC: G06F21/85 ,  G06F21/60

CPC classification number: G06F21/85 ,  G06F11/10 ,  G06F13/362 ,  G06F13/40 ,  G06F21/602 ,  G06F21/606 ,  G06F21/755 ,  H03M13/11 ,  H04K1/00 ,  H04L1/0063

Abstract: The embodiments of the present invention disclose a bus security protection apparatus, including: a first check module, configured to check operation data, to generate a first check code; a first conversion module, configured to perform an exclusive-OR logical operation on the operation data and a polarity indication signal, to obtain polarity reversal data; a first encryption/decryption module, configured to perform an exclusive-OR logical operation on the polarity reversal data and preset scrambling data, to obtain encrypted data; a second encryption/decryption module, configured to perform an exclusive-OR logical operation on the encrypted data and the preset scrambling data, to obtain decrypted data; a second conversion module, configured to perform an exclusive-OR logical operation on the decrypted data and the polarity indication signal, to obtain decrypted conversion data; and a second check module, configured to: check the decrypted conversion data, to generate a second check code.