公开(公告)号：US06754814B1

公开(公告)日：2004-06-22

申请号：US09461424

申请日：1999-12-16

申请人： Hiroki Narita ,  Aiichiro Inoue

发明人： Hiroki Narita ,  Aiichiro Inoue

IPC分类号： G06F900

CPC分类号： G06F9/24 ,  G06F9/30101 ,  G06F9/30145

摘要： An instruction processing apparatus using a microprogram instruction which implements re-reading operation. The instruction execution apparatus is provided with a queue stack, a unit halting requests for reading subsequent instructions at the instruction of a microprogram, and a unit releasing this halt. Further, by instruction the reading of the subsequent instructions using the microprogram control information, it becomes possible to simultaneously execute the microprogram and instruction re-reading processing. Because the Program Status Word Instruction Address (PSWIAR) of the load control (LCTL) plus the instruction length of the PSWIAR makes an instruction fetch address of the LCTL, the hardware of the instruction re-read address production circuit (which is a part of the instruction processing circuit) can be used. This reduces the: T-cycle instruction address register (TIAR), T-cycle instruction length code (TILC), A-cycle instruction address register (AIAR), the A-cycle instruction length code (AILC), and an adder for adding the TILC with the TIAR.

摘要翻译： 一种使用微程序指令进行再读操作的指令处理装置。 指令执行装置设置有队列堆栈，在微程序的指令中停止读取后续指令的请求单元，以及释放该暂停的单元。 此外，通过指令使用微程序控制信息读取后续指令，可以同时执行微程序和指令重新读取处理。 由于负载控制（LCTL）的程序状态字指令地址（PSWIAR）加上PSWIAR的指令长度使得LCTL的指令获取地址指令重新读取地址生成电路的硬件（它是 指令处理电路）。 这减少了：T周期指令地址寄存器（TIAR），T周期指令长度代码（TILC），A周期指令地址寄存器（AIAR），A周期指令长度代码（AILC）和加法器 TILC与TIAR。

公开(公告)号：US06637009B2

公开(公告)日：2003-10-21

申请号：US09946484

申请日：2001-09-06

申请人： Hiroki Narita

发明人： Hiroki Narita

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method and device are disclosed for easy and proper optimization of a logic circuit having a hierarchical structure. A limit value storage unit stores in advance target delay values that are the limit values of delay times. A flip-flop extraction unit extracts flip-flops included in the logic circuit that is the object of optimization and that is stored in a logic circuit storage unit. A hierarchy modification unit traces the logic circuit in the opposite direction of signal flow from an external output terminal of the logic circuit or the input of an extracted flip-flop until reaching an external input terminal of the logic circuit or another flip-flop and then modifies the hierarchical structure of the logic circuit to a structure constituted by hierarchical circuits that are each including logic elements that were passed through and flip-flops that were reached. A hierarchical circuit merge unit joins hierarchical circuits that include the same flip-flop. A logic optimization execution unit optimizes each of the hierarchical circuits such that their delay times satisfy the target delay values.

公开(公告)号：US06571377B2

公开(公告)日：2003-05-27

申请号：US09796798

申请日：2001-03-02

申请人： Hiroki Narita

发明人： Hiroki Narita

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A circuit design apparatus of the present invention includes a first element which divides a circuit into a plurality of divided circuits and a second element which calculates individual constraint values of the divided circuits, respectively, using a constraint value of the circuit. A third element of the present invention optimizes each of the divided circuits based on the corresponding individual constraint values. A fourth element merges the divided circuits, which are optimized by the third element, into one circuit.

摘要翻译： 本发明的电路设计装置包括将电路分成多个分割电路的第一元件和分别使用该电路的约束值计算划分电路的各个约束值的第二元件。 本发明的第三要素基于相应的各个约束值优化每个分割电路。 第四个元件将由第三元件优化的分频电路合并成一个电路。