公开(公告)号：US20240006918A1

公开(公告)日：2024-01-04

申请号：US17853575

申请日：2022-06-29

Applicant: Halo Microelectronics International

Inventor： Rui Liu ,  Lijie Zhao ,  Feng Zhou

IPC: H02J50/12 ,  H04B5/00 ,  H02M1/00 ,  H04L27/04

CPC classification number: H02J50/12 ,  H04B5/0037 ,  H04L27/04 ,  H02M1/0025 ,  H04B5/0075

Abstract: In an embodiment method, an envelope voltage of a resonant capacitor of a wireless power receiver in a wireless charging system may be detected at an output node. One or more parameters of the wireless power receiver may be adjusted in order keep the envelope voltage within a pre-determined voltage range. The one or more parameters includes a capacitance across a receiving coil and the resonant capacitor, or a current of a sub-circuit connected between the output node and a ground. An amplitude shift keying (ASK) carrier signal may be detected at a wireless power transmitter of the wireless charging system and attenuated. A demodulated ASK signal may be generated from the attenuated ASK carrier signal based on peak values of the attenuated ASK carrier signal and a zero-crossing signal generated from the attenuated ASK carrier signal.

公开(公告)号：US20230102084A1

公开(公告)日：2023-03-30

申请号：US18062623

申请日：2022-12-07

Applicant: Halo Microelectronics International

Inventor： Lijie Zhao ,  Kien Chan Vi ,  Hai Tao

IPC: H03M1/06

Abstract: An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

公开(公告)号：US11791830B2

公开(公告)日：2023-10-17

申请号：US18062623

申请日：2022-12-07

Applicant: Halo Microelectronics International

Inventor： Lijie Zhao ,  Kien Chan Vi ,  Hai Tao

IPC: H03M1/06 ,  H03M1/20 ,  H03M1/46 ,  H03M1/40

CPC classification number: H03M1/0607 ,  H03M1/201 ,  H03M1/40 ,  H03M1/46

Abstract: An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

公开(公告)号：US20230044360A1

公开(公告)日：2023-02-09

申请号：US17393875

申请日：2021-08-04

Applicant: Halo Microelectronics International

Inventor： Lijie Zhao ,  Kenneth Chung-Yin Kwok ,  Suming Lai ,  Zhao Fang

IPC: H01L27/06 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/872 ,  H03K17/0814

Abstract: An apparatus includes a first drain/source region and a second drain/source region surrounded by an isolation ring formed over a substrate, the isolation ring formed being configured to be floating, and a first diode connected between the substrate and the isolation ring, wherein the first diode is a Schottky diode.

公开(公告)号：US20220247419A1

公开(公告)日：2022-08-04

申请号：US17644589

申请日：2021-12-16

Applicant: Halo Microelectronics International

Inventor： Lijie Zhao ,  Kien Chan Vi ,  Hai Tao

IPC: H03M1/06

Abstract: A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2(K+1) steps, each of which has a value equal to an integer multiplying 2(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2(K+1) number of N-bit digital signals based on the at least 2(K+1) steps of the digitally controlled offset voltage, summing the at least the 2(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

公开(公告)号：US11722143B2

公开(公告)日：2023-08-08

申请号：US17644589

申请日：2021-12-16

Applicant: Halo Microelectronics International

Inventor： Lijie Zhao ,  Kien Chan Vi ,  Hai Tao

IPC: H03M1/06 ,  H03M1/20 ,  H03M1/46 ,  H03M1/40

CPC classification number: H03M1/0607 ,  H03M1/201 ,  H03M1/40 ,  H03M1/46

Abstract: A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2(K+1) steps, each of which has a value equal to an integer multiplying 2(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2(K+1) number of N-bit digital signals based on the at least 2(K+1) steps of the digitally controlled offset voltage, summing the at least the 2(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.