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公开(公告)号：US11722143B2
公开(公告)日：2023-08-08
申请号：US17644589
申请日：2021-12-16
Applicant: Halo Microelectronics International
Inventor： Lijie Zhao , Kien Chan Vi , Hai Tao
CPC classification number: H03M1/0607 , H03M1/201 , H03M1/40 , H03M1/46
Abstract: A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2(K+1) steps, each of which has a value equal to an integer multiplying 2(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2(K+1) number of N-bit digital signals based on the at least 2(K+1) steps of the digitally controlled offset voltage, summing the at least the 2(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.
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公开(公告)号：US20220128632A1
公开(公告)日：2022-04-28
申请号：US17484269
申请日：2021-09-24
Applicant: Halo Microelectronics International
Inventor： Suming Lai , Kenneth Chung-Yin Kwok , Kien Chan Vi
Abstract: A method includes connecting an input voltage bus of a switched capacitor converter to a power source through a load switch, in a first short circuit testing step, determining whether the load switch or a second switch is shorted by comparing a voltage on the input voltage bus with a first predetermined voltage reference, after passing the first short circuit testing step, in a second short circuit testing step, determining whether a first switch or a fourth switch is shorted by comparing a voltage on the common node of the third switch and the fourth switch with a second predetermined voltage reference, and after passing the second short circuit testing step, in a third short circuit testing step, determining whether a third switch is shorted by comparing the voltage on the common node of the third switch and the fourth switch with a third predetermined voltage reference.
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Patent Agency Ranking
公开(公告)号：US20230375641A1
公开(公告)日：2023-11-23
申请号：US18229991
申请日：2023-08-03
Applicant: Halo Microelectronics International
Inventor： Suming Lai , Kenneth Chung-Yin Kwok , Kien Chan Vi , Anan Xiang , Songnan Yang
CPC classification number: G01R31/52 , G01R31/40 , H02M3/07 , H02J7/007 , H02J2207/20
Abstract: A method includes connecting an output of a switched capacitor converter to a battery, the switched capacitor converter comprising a first switch, a second switch, a third switch and an upper circuit connected in series, and a flying capacitor connected between a common node of the first switch and the second switch, and a common node of the third switch and the upper circuit, in a first short circuit testing step, determining whether the third switch is shorted by comparing a voltage on the common node of the third switch and the upper circuit with a first predetermined voltage reference, and in a second short circuit testing step, determining whether the first switch and the second switch are shorted by comparing a voltage on the common node of the first switch and the second switch with a second predetermined voltage reference and a third predetermined voltage reference, respectively.
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公开(公告)号：US20230102084A1
公开(公告)日：2023-03-30
申请号：US18062623
申请日：2022-12-07
Applicant: Halo Microelectronics International
Inventor： Lijie Zhao , Kien Chan Vi , Hai Tao
IPC: H03M1/06
Abstract: An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.
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公开(公告)号：US11791830B2
公开(公告)日：2023-10-17
申请号：US18062623
申请日：2022-12-07
Applicant: Halo Microelectronics International
Inventor： Lijie Zhao , Kien Chan Vi , Hai Tao
CPC classification number: H03M1/0607 , H03M1/201 , H03M1/40 , H03M1/46
Abstract: An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.
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公开(公告)号：US11740300B2
公开(公告)日：2023-08-29
申请号：US17484269
申请日：2021-09-24
Applicant: Halo Microelectronics International
Inventor： Suming Lai , Kenneth Chung-Yin Kwok , Kien Chan Vi
Abstract: A method includes connecting an input voltage bus of a switched capacitor converter to a power source through a load switch, in a first short circuit testing step, determining whether the load switch or a second switch is shorted by comparing a voltage on the input voltage bus with a first predetermined voltage reference, after passing the first short circuit testing step, in a second short circuit testing step, determining whether a first switch or a fourth switch is shorted by comparing a voltage on the common node of the third switch and the fourth switch with a second predetermined voltage reference, and after passing the second short circuit testing step, in a third short circuit testing step, determining whether a third switch is shorted by comparing the voltage on the common node of the third switch and the fourth switch with a third predetermined voltage reference.
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公开(公告)号：US20220247419A1
公开(公告)日：2022-08-04
申请号：US17644589
申请日：2021-12-16
Applicant: Halo Microelectronics International
Inventor： Lijie Zhao , Kien Chan Vi , Hai Tao
IPC: H03M1/06
Abstract: A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2(K+1) steps, each of which has a value equal to an integer multiplying 2(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2(K+1) number of N-bit digital signals based on the at least 2(K+1) steps of the digitally controlled offset voltage, summing the at least the 2(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.
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