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公开(公告)号：US20230102084A1
公开(公告)日：2023-03-30
申请号：US18062623
申请日：2022-12-07
Applicant: Halo Microelectronics International
Inventor： Lijie Zhao , Kien Chan Vi , Hai Tao
IPC: H03M1/06
Abstract: An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.
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Patent Agency Ranking
公开(公告)号：US20220302849A1
公开(公告)日：2022-09-22
申请号：US17205596
申请日：2021-03-18
Applicant: Halo Microelectronics International
Inventor： Hai Tao , Chih-Hsien Hsieh , Kai-Fang Wei , Zhibo Tao
Abstract: A control circuit is configured to control a flyback circuit comprising a primary-side switch, a secondary-side rectifier and a transformer. The control circuit comprises a feedback control circuit configured to generate a secondary-side control signal based on a current ripple signal of the transformer, and at least one of a direct-current component of an output voltage signal and a direct-current component of an output current signal of a secondary side of the flyback circuit, wherein the secondary-side control signal is configured to control a turn-off of the secondary-side rectifier, an isolated transmission circuit coupled to the feedback control circuit and configured to generate a first primary-side control signal based on the secondary-side control signal, and a primary control circuit coupled to the isolated transmission circuit and configured to control a turn-on of the primary-side switch in response to receiving the first primary-side control signal.
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公开(公告)号：US11722143B2
公开(公告)日：2023-08-08
申请号：US17644589
申请日：2021-12-16
Applicant: Halo Microelectronics International
Inventor： Lijie Zhao , Kien Chan Vi , Hai Tao
CPC classification number: H03M1/0607 , H03M1/201 , H03M1/40 , H03M1/46
Abstract: A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2(K+1) steps, each of which has a value equal to an integer multiplying 2(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2(K+1) number of N-bit digital signals based on the at least 2(K+1) steps of the digitally controlled offset voltage, summing the at least the 2(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.
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公开(公告)号：US11689113B2
公开(公告)日：2023-06-27
申请号：US17205596
申请日：2021-03-18
Applicant: Halo Microelectronics International
Inventor： Hai Tao , Chih-Hsien Hsieh , Kai-Fang Wei , Zhibo Tao
CPC classification number: H02M3/33592 , H02J7/007 , H02M1/0019 , H02M3/33523 , H02J2207/20
Abstract: A control circuit is configured to control a flyback circuit comprising a primary-side switch, a secondary-side rectifier and a transformer. The control circuit comprises a feedback control circuit configured to generate a secondary-side control signal based on a current ripple signal of the transformer, and at least one of a direct-current component of an output voltage signal and a direct-current component of an output current signal of a secondary side of the flyback circuit, wherein the secondary-side control signal is configured to control a turn-off of the secondary-side rectifier, an isolated transmission circuit coupled to the feedback control circuit and configured to generate a first primary-side control signal based on the secondary-side control signal, and a primary control circuit coupled to the isolated transmission circuit and configured to control a turn-on of the primary-side switch in response to receiving the first primary-side control signal.
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公开(公告)号：US11791830B2
公开(公告)日：2023-10-17
申请号：US18062623
申请日：2022-12-07
Applicant: Halo Microelectronics International
Inventor： Lijie Zhao , Kien Chan Vi , Hai Tao
CPC classification number: H03M1/0607 , H03M1/201 , H03M1/40 , H03M1/46
Abstract: An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.
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公开(公告)号：US20220247419A1
公开(公告)日：2022-08-04
申请号：US17644589
申请日：2021-12-16
Applicant: Halo Microelectronics International
Inventor： Lijie Zhao , Kien Chan Vi , Hai Tao
IPC: H03M1/06
Abstract: A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2(K+1) steps, each of which has a value equal to an integer multiplying 2(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2(K+1) number of N-bit digital signals based on the at least 2(K+1) steps of the digitally controlled offset voltage, summing the at least the 2(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.
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