公开(公告)号：US20200334322A1

公开(公告)日：2020-10-22

申请号：US16915915

申请日：2020-06-29

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Haoxun Lin ,  Fan Zhu

IPC: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

公开(公告)号：US20230205530A1

公开(公告)日：2023-06-29

申请号：US18172492

申请日：2023-02-22

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ruoyu Zhou ,  Fan Zhu ,  Wenbo Sun ,  Xiping Zhou

IPC: G06F9/30

CPC classification number: G06F9/30163 ,  G06F9/30007

Abstract: This application provides a graph instruction processing method and apparatus. The method is applied to a processor, and includes: detecting whether a first input and a second input of a first graph instruction are in a ready-to-complete state, where the first input and/or the second input are or is a dynamic data input or dynamic data inputs of the first graph instruction.

公开(公告)号：US20200026746A1

公开(公告)日：2020-01-23

申请号：US16586164

申请日：2019-09-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jiajin Tu ,  Fan Zhu ,  Qiang Lin ,  Hu Liu

IPC: G06F17/16

Abstract: A matrix and vector multiplication operation method includes obtaining first indication information of a matrix element, reading a matrix element value of a non-zero element from a preset matrix based on the first indication information, and determining a first location mark code of the read matrix element value, obtaining second indication information of a vector element, reading, from input vector data based on the second indication information, a vector element value of a second location mark code corresponding to the first location mark code, and obtaining a multiplication operation value of the matrix element value and the vector element value.

公开(公告)号：US12124851B2

公开(公告)日：2024-10-22

申请号：US18067538

申请日：2022-12-16

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ruoyu Zhou ,  Fan Zhu ,  Wenbo Sun ,  Xiping Zhou

IPC: G06F9/30

CPC classification number: G06F9/30058

Abstract: Disclosed are a graph instruction processing method and apparatus, which relates to the field of computer technologies One example method includes: detecting whether a first graph instruction has a conditional instruction element; and when the first graph instruction has the conditional instruction element, determining that the first graph instruction is a conditional execution instruction, and processing the first graph instruction when both data flow information and control flow information of the first graph instruction are in a ready state; or when the first graph instruction does not have a conditional instruction element, determining that the first graph instruction is a non-conditional execution instruction, and processing the first graph instruction when data flow information of the first graph instruction is in a ready state.

公开(公告)号：US20230297385A1

公开(公告)日：2023-09-21

申请号：US18312365

申请日：2023-05-04

Applicant: Huawei Technologies Co., Ltd.

Inventor： Fan Zhu ,  Ruoyu Zhou ,  Wenbo Sun ,  Xiping Zhou

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30047 ,  G06F9/30189

Abstract: A graphflow apparatus includes an information buffer (IB) and a load queue (LQ). The IB is configured to cache an instruction queue. The LQ is used to cache a read instruction queue. The IB includes a speculative bit and a speculative identity (ID) field. The speculative bit indicates whether a current instruction is a speculatively-executable instruction. The speculative ID field stores a speculative ID of one speculative operation on the current instruction.

公开(公告)号：US20220245218A1

公开(公告)日：2022-08-04

申请号：US17725492

申请日：2022-04-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Hou Fun Lam ,  Fan Zhu

IPC: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

公开(公告)号：US12086592B2

公开(公告)日：2024-09-10

申请号：US18070781

申请日：2022-11-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xiping Zhou ,  Ruoyu Zhou ,  Fan Zhu ,  Wenbo Sun

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30076 ,  G06F9/30087 ,  G06F9/3836

Abstract: This application discloses a processor, a processing method, and a related device. The processor includes a processor core. The processor core includes an instruction dispatching unit and a graph flow unit and at least one general-purpose operation unit that are connected to the instruction dispatching unit. The instruction dispatching unit is configured to: allocate a general-purpose calculation instruction in a decoded to-be-executed instruction to the at least one general-purpose calculation unit, and allocate a graph calculation control instruction in the decoded to-be-executed instruction to the graph calculation unit, where the general-purpose calculation instruction is used to instruct to execute a general-purpose calculation task, and the graph calculation control instruction is used to instruct to execute a graph calculation task. The at least one general-purpose operation unit is configured to execute the general-purpose calculation instruction. The graph flow unit is configured to execute the graph calculation control instruction.

公开(公告)号：US11934481B2

公开(公告)日：2024-03-19

申请号：US17725492

申请日：2022-04-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Hou Fun Lam ,  Fan Zhu

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

公开(公告)号：US11334648B2

公开(公告)日：2022-05-17

申请号：US16915915

申请日：2020-06-29

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Hou Fun Lam ,  Fan Zhu

IPC: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.