CHIP AND PREPARATION METHOD THEREOF, AND ELECTRONIC DEVICE

    公开(公告)号:US20250038075A1

    公开(公告)日:2025-01-30

    申请号:US18911277

    申请日:2024-10-10

    Abstract: A integrated circuit (IC) chip includes a dielectric layer and a first conductive pillar disposed in the dielectric layer. The first conductive pillar runs through the dielectric layer in a thickness direction of the dielectric layer. The chip further includes a first conductive pattern and a second conductive pattern that are located on two opposite sides of the first conductive pillar and are coupled to the first conductive pillar. The first conductive pillar includes a metal pillar and a metal compound layer. The metal compound layer is located between the metal pillar and the dielectric layer and covers a part of a side surface of the metal pillar. The first conductive pillar is directly in contact with the dielectric layer, and no barrier layer is disposed between the first conductive pillar and the dielectric layer.

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