公开(公告)号：US20140110808A1

公开(公告)日：2014-04-24

申请号：US14138950

申请日：2013-12-23

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Kazuhisa YAMAMURA ,  Akira SAKAMOTO ,  Terumasa NAGANO ,  Yoshitaka ISHIKAWA ,  Satoshi KAWAI

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/1463 ,  H01L27/14649 ,  H01L27/14689 ,  H01L31/0232 ,  H01L31/0236 ,  H01L31/02363 ,  H01L31/035281 ,  H01L31/103 ,  H01L31/107 ,  H01L2224/48091 ,  Y02E10/50 ,  H01L2924/00014

Abstract: A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p− type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CH. The p− type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.

Abstract translation: 光电二极管阵列PDA1设置有基板S，其中多个受光通道CH具有n型半导体层32.光电二极管阵列PDA1设置有形成在n型半导体层32上的p型半导体层33，电阻 设置在相应的光检测通道CH上，每个具有连接到信号导线23的一个端部，以及形成在多个光电检测通道CH之间的n型分离部分40。 p型半导体层33在与n型半导体层32的界面处形成pn结，并且具有多个乘法区域AM，用于对应于各个受光通道而与检测目标光入射产生的载流子的雪崩乘法。 在n型半导体层32的表面上形成不规则的凹凸10，并且该表面被光学曝光。

公开(公告)号：US20170162726A1

公开(公告)日：2017-06-08

申请号：US15434373

申请日：2017-02-16

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Kazuhisa YAMAMURA ,  Akira SAKAMOTO ,  Terumasa NAGANO ,  Yoshitaka ISHIKAWA ,  Satoshi KAWAI

IPC: H01L31/0236 ,  H01L31/18 ,  H01L31/107 ,  H01L27/144 ,  H01L31/028

CPC classification number: H01L31/02366 ,  H01L27/1446 ,  H01L27/1464 ,  H01L31/0236 ,  H01L31/02363 ,  H01L31/028 ,  H01L31/107 ,  H01L31/1804 ,  Y02E10/547

Abstract: A p− type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p− type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p− type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p− type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.

公开(公告)号：US20150214395A1

公开(公告)日：2015-07-30

申请号：US14683524

申请日：2015-04-10

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Kazuhisa YAMAMURA ,  Akira SAKAMOTO ,  Terumasa NAGANO ,  Yoshitaka ISHIKAWA ,  Satoshi KAWAI

IPC: H01L31/0236 ,  H01L27/146 ,  H01L31/107

CPC classification number: H01L31/02366 ,  H01L27/1446 ,  H01L27/1464 ,  H01L31/0236 ,  H01L31/02363 ,  H01L31/028 ,  H01L31/107 ,  H01L31/1804 ,  Y02E10/547

Abstract: A p− type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p− type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p− type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p− type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.

Abstract translation: p型半导体衬底20具有彼此相对并包括感光区域21的第一主表面20a和第二主表面20b。感光区域21由n +型杂质区域23，p +型杂质区域25 以及在p型半导体衬底20中施加偏置电压而被耗尽的区域。在p型半导体衬底20的第二主表面20b中形成不规则的凹凸10.在 p型半导体衬底20的第二主表面20b侧和与感光区域21相对的累积层37中的区域被光学曝光。