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    Phase comparison method, phase comparison circuit, and phase locked loop (PLL) type circuit
    1.
    发明授权
    Phase comparison method, phase comparison circuit, and phase locked loop (PLL) type circuit 失效
    相位比较法，相位比较电路和锁相环（PLL）型电路

    公开(公告)号：US06809597B2

    公开(公告)日：2004-10-26

    申请号：US10400105

    申请日：2003-03-26

    申请人： Glenn Keiji Murata

    发明人： Glenn Keiji Murata

    IPC分类号： H03F2100

    CPC分类号： H03D13/003 ,  H03L7/087 ,  H03L7/091 ,  H03L7/18 ,  H03L2207/06

    摘要： A phase comparison circuit for generating control voltages for a number of varactors of a phase locked loop (PLL) circuit has been disclosed. According to a particular embodiment, a number of phase difference detection circuits (101, 102 and 103) can be successively activated in response to a set of activation signals to generate output voltage signals (Vtunei). Output voltage signals (Vtunei) can vary according to an elapsed period time, and thus represent a phase difference. Each phase difference detection circuit (101, 102 and 103) can activate a trigger signal (Trg) when an internal voltage signal equals a predetermined value. A main signal (SIG) can be input as an activation signal to a first stage phase difference detection circuit (101). A trigger signal from a first stage phase difference detection circuit (101) can be input as an activation signal to a subsequent stage phase difference detection circuit (102). Phase difference detection circuits (101, 102 and 103) can be deactivated in response to an output signal (out) generated in response to a reference signal (REF), and provide output voltages (Vtunei) which can represent a phase difference between reference signal (REF) and a main signal (SIG).

    摘要翻译： 已经公开了用于产生多个锁相环（PLL）电路的变容二极管的控制电压的相位比较电路。 根据特定实施例，可以响应于一组激活信号连续激活多个相位差检测电路（101,102和103），以产生输出电压信号（Vtunei）。 输出电压信号（Vtunei）可以根据经过的周期时间而变化，因此表示相位差。 当内部电压信号等于预定值时，每个相位差检测电路（101,102和103）可激活触发信号（Trg）。 可以将主信号（SIG）作为激活信号输入到第一级相位差检测电路（101）。 可以将来自第一级相位差检测电路（101）的触发信号作为激活信号输入到后级相位差检测电路（102）。 相位差检测电路（101,102和103）可响应于响应于参考信号（REF）产生的输出信号（out）而被去激活，并且提供输出电压（Vtunei），其可以表示参考信号 （REF）和主信号（SIG）。

    Clock supply bias circuit and single-phase clock drive frequency dividing circuit using the same
    2.
    发明授权
    Clock supply bias circuit and single-phase clock drive frequency dividing circuit using the same 失效
    时钟供电偏置电路和单相时钟驱动分频电路使用相同

    公开(公告)号：US06765418B2

    公开(公告)日：2004-07-20

    申请号：US10099276

    申请日：2002-03-14

    申请人： Glenn Keiji Murata

    发明人： Glenn Keiji Murata

    IPC分类号： H03K2500

    CPC分类号： H03K21/02

    摘要： A single-phase clock CLK0 is divided into a clock signal CLK1 to drive nMOS transistor and a clock signal CLK2 to drive pMOS transistor, and the resulting clock signals are inputted to DFF circuits 1 to 3 constituting a frequency dividing circuit, making gms of nMOS and pMOS transistors larger than that could be achieved using the conventional technique. Therefore, frequency dividing performance can be greatly improved in comparison with that achieved using conventional technology.

    摘要翻译： 单相时钟CLK0被分成时钟信号CLK1以驱动nMOS晶体管和时钟信号CLK2以驱动pMOS晶体管，并且所得到的时钟信号被输入到构成分频电路的DFF电路1至3，使得gms为nMOS 并且使用传统技术可以实现比这更大的pMOS晶体管。 因此，与使用传统技术的分频性能相比，可以大大提高分频性能。