公开(公告)号：US09510021B2

公开(公告)日：2016-11-29

申请号：US14286822

申请日：2014-05-23

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Seunghyun Cho ,  Hyun Mi Kim ,  Kyung Jin Byun ,  Nak Woong Eum

IPC: H04N19/86 ,  H04N19/423

CPC classification number: H04N19/86 ,  H04N19/423

Abstract: Provided is a method for a plurality of processing elements to filter a plurality of pixel blocks in a plurality of picture partitions for a single frame image. The method for filtering pixel blocks includes: checking the status of a second boundary pixel block adjacent to a picture partition boundary, the second boundary pixel block being one of a plurality of pixel blocks in a second picture partition and neighboring a first boundary pixel block in a first picture partition, the first boundary pixel block neighboring the picture partition boundary; selecting a filtering area for the first boundary pixel block based on the status of the second boundary pixel block; and filtering the filtering area for the first boundary pixel block.

Abstract translation: 提供了一种用于多个处理元件的滤波方法，用于对用于单帧图像的多个图像分区中的多个像素块进行滤波。 用于滤波像素块的方法包括：检查与图像分区边界相邻的第二边界像素块的状态，第二边界像素块是第二图像分区中的多个像素块中的一个，并且邻近第一边界像素块 第一图像分区，与图像分区边界相邻的第一边界像素块; 基于第二边界像素块的状态为第一边界像素块选择滤波区域; 并对第一边界像素块的滤波区域进行滤波。

公开(公告)号：US12210952B2

公开(公告)日：2025-01-28

申请号：US16201871

申请日：2018-11-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-Su Kwon ,  Chan Kim ,  Hyun Mi Kim ,  Jeongmin Yang ,  Chun-Gi Lyuh ,  Jaehoon Chung ,  Yong Cheol Peter Cho

IPC: G06N3/04

Abstract: A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.

公开(公告)号：US11847465B2

公开(公告)日：2023-12-19

申请号：US17533788

申请日：2021-11-23

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Chun-Gi Lyuh ,  Hyun Mi Kim ,  Young-Su Kwon ,  Jin Ho Han

IPC: G06F9/38 ,  G06F9/355 ,  G06F12/02

CPC classification number: G06F9/3895 ,  G06F9/355 ,  G06F12/0207

Abstract: Disclosed is a parallel processor. The parallel processor includes a processing element array including a plurality of processing elements arranged in rows and columns, a row memory group including row memories corresponding to rows of the processing elements, a column memory group including column memories corresponding to columns of the processing elements, and a controller to generate a first address and a second address, to send the first address to the row memory group, and to send the second address to the column memory group. The controller supports convolution operations having mutually different forms, by changing a scheme of generating the first address.

公开(公告)号：US11507429B2

公开(公告)日：2022-11-22

申请号：US16038243

申请日：2018-07-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Chun-Gi Lyuh ,  Young-Su Kwon ,  Chan Kim ,  Hyun Mi Kim ,  Jeongmin Yang ,  Jaehoon Chung ,  Yong Cheol Peter Cho

IPC: G06N3/063 ,  G06F15/80 ,  G06F9/50 ,  G06N5/04 ,  G06F9/38 ,  G06F9/30

Abstract: Provided is a neural network accelerator which performs a calculation of a neural network provided with layers, the neural network accelerator including a kernel memory configured to store kernel data related to a filter, a feature map memory configured to store feature map data which are outputs of the layers, and a Processing Element (PE) array including PEs arranged along first and second directions, wherein each of the PEs performs a calculation using the feature map data transmitted in the first direction from the feature map memory and the kernel data transmitted in the second direction from the kernel memory, and transmits a calculation result to the feature map memory in a third direction opposite to the first direction.