公开(公告)号：US09379824B2

公开(公告)日：2016-06-28

申请号：US14551826

申请日：2014-11-24

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong-Seok Choi ,  Hyuk-Je Kwon ,  Gyung-Ock Kim

IPC: H04B10/80

CPC classification number: H04B10/801

Abstract: Disclosed are an apparatus and method for interfacing between a central processing unit (CPU) and a main memory unit, whereby a shared cache memory unit and the main memory unit are connected to each other using one optical signal transmission line. The apparatus for interfacing between the CPU and the main memory unit includes: a master optical connection protocol engine, converting operation control signals received from a shared cache memory unit of the CPU into serial signals; a first electrical-to-optical (E/O) converter, converting the serial signals converted by the master optical connection protocol engine into optical signals; a second E/O converter, converting the optical signals converted by the first E/O converter into serial signals; a slave optical connection protocol engine, converting the serial signals converted by the second E/O converter into operation control signals; and a memory controller having access to the main memory unit.

Abstract translation: 公开了一种用于在中央处理单元（CPU）和主存储单元之间进行接口的装置和方法，由此共享高速缓冲存储器单元和主存储器单元使用一个光信号传输线相互连接。 用于在CPU和主存储器单元之间进行接口的装置包括：主光连接协议引擎，将从CPU的共享高速缓冲存储器单元接收的操作控制信号转换为串行信号; 第一电光转换器，将由主光连接协议引擎转换的串行信号转换为光信号; 第二E / O转换器，将由第一E / O转换器转换的光信号转换为串行信号; 从属光连接协议引擎，将由第二E / O转换器转换的串行信号转换成操作控制信号; 以及具有访问主存储器单元的存储器控​​制器。

公开(公告)号：US20150006806A1

公开(公告)日：2015-01-01

申请号：US14244047

申请日：2014-04-03

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyuk-Je Kwon ,  Young-Seok Choi ,  Sung-Nam Kim ,  Gyung-Ock Kim

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C5/04 ,  G11C11/4093

Abstract: Disclosed are a double data rate synchronous dynamic random access memory module and a configuring method thereof. The DDR SDRAM module in accordance with an embodiment of the present invention includes: a plurality of memory chips; and a serial transceiver portion configured to serially receive first serial data including a control signal and data transferred from outside for the plurality of memory chips and to provide the control signal and the data included in the serially received first serial data to the plurality of memory chips.

Abstract translation: 公开了一种双倍数据速率同步动态随机存取存储器模块及其配置方法。 根据本发明的实施例的DDR SDRAM模块包括：多个存储器芯片; 以及串行收发器部分，其被配置为串行地接收包括控制信号的第一串行数据和从多个存储器芯片从外部传送的数据，并且将包括在串行接收的第一串行数据中的控制信号和数据提供给多个存储器芯片 。