公开(公告)号：US20220180162A1

公开(公告)日：2022-06-09

申请号：US17544224

申请日：2021-12-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin-Ho HAN ,  Young-Su KWON ,  Mi-Young LEE ,  Joo-Hyun LEE ,  Yong-Cheol CHO

IPC: G06N3/063

Abstract: Disclosed herein is an AI accelerator. The AI accelerator includes processors, each performing a deep-learning operation using multiple threads; and a cache memory including an L0 instruction cache for providing instructions to the processors and an L1 cache mapped to the multiple areas of mapped memory.

公开(公告)号：US20160334467A1

公开(公告)日：2016-11-17

申请号：US15154829

申请日：2016-05-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong-Cheol CHO ,  Young-Su KWON

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G06F17/50 ,  G06F11/261 ,  G06F17/5022 ,  G06F17/5045 ,  G06F2217/70

Abstract: Disclosed herein is a method and apparatus for injecting a fault and analyzing fault tolerance. The fault tolerance analysis apparatus extracts design information from a design. The fault tolerance analysis apparatus may inject a fault into a simulation of the design based on the extracted design information and parameters, and analyzes an influence of the fault on the simulation. Accordingly, in accordance with the fault tolerance analysis apparatus, fault tolerance for the fault injected into the simulation is analyzed, and the effect of the fault tolerance mechanism provided in the design is analyzed.

Abstract translation: 这里公开了一种用于注入故障并分析容错的方法和装置。 容错分析设备从设计中提取设计信息。 容错分析装置可以根据提取的设计信息和参数将故障注入到设计的仿真中，并分析故障对仿真的影响。 因此，根据容错分析装置，分析了注入到模拟中的故障的容错性，分析了设计中提供的容错机理的影响。

公开(公告)号：US20230259581A1

公开(公告)日：2023-08-17

申请号：US18109690

申请日：2023-02-14

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Won JEON ,  Young-Su KWON ,  Ju-Yeob KIM ,  Hyun-Mi KIM ,  Hye-Ji KIM ,  Chun-Gi LYUH ,  Mi-Young LEE ,  Jae-Hoon CHUNG ,  Yong-Cheol CHO ,  Jin-Ho HAN

IPC: G06F17/16 ,  G06F5/01

CPC classification number: G06F17/16 ,  G06F5/012

Abstract: Disclosed herein is a method for outer-product-based matrix multiplication for a floating-point data type includes receiving first floating-point data and second floating-point data and performing matrix multiplication on the first floating-point data and the second floating-point data, and the result value of the matrix multiplication is calculated based on the suboperation result values of floating-point units.