公开(公告)号：US20180034686A1

公开(公告)日：2018-02-01

申请号：US15221538

申请日：2016-07-27

Applicant: CISCO TECHNOLOGY, INC

Inventor： Ramanan Vaidyanathan ,  Ajay Modi ,  Azeem Suleman ,  Krishna Doddapaneni ,  Sarang Dharmapurikar ,  Ganlin Wu

IPC: H04L12/24 ,  G06F11/07 ,  H04B17/17 ,  H04L29/06 ,  H04L12/947

CPC classification number: H04L41/0677 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  H04B17/17 ,  H04L41/0873 ,  H04L43/08 ,  H04L49/25 ,  H04L69/16 ,  H04L69/22

Abstract: Systems, methods, and computer-readable media for improving debugging and troubleshooting of datacenter networks, and more particularly improving the speed of forwarding/data path related problems without going into ASIC level debugging. A switch could, for example, have a processor which communicates with an ASIC. The processor can receive flow information and a notification from the ASIC, the notification indicating a predefined error condition has been identified in a packet. The processor can modify the ASIC programming based on the notification, such that the ASIC records additional, more-detailed, flow information for the switch. The processor can then receive, from the modified ASIC, the additional flow information. The additional flow information can then be used (either by the processor or by an operator) to identify the exact reason for the errors in the flow path.

公开(公告)号：US10142168B2

公开(公告)日：2018-11-27

申请号：US15221538

申请日：2016-07-27

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Ramanan Vaidyanathan ,  Ajay Modi ,  Azeem Suleman ,  Krishna Doddapaneni ,  Sarang Dharmapurikar ,  Ganlin Wu

IPC: H04L12/24 ,  H04L29/06 ,  H04L12/947 ,  H04B17/17 ,  G06F11/07 ,  H04L12/26

Abstract: Systems, methods, and computer-readable media for improving debugging and troubleshooting of datacenter networks, and more particularly improving the speed of forwarding/data path related problems without going into ASIC level debugging. A switch could, for example, have a processor which communicates with an ASIC. The processor can receive flow information and a notification from the ASIC, the notification indicating a predefined error condition has been identified in a packet. The processor can modify the ASIC programming based on the notification, such that the ASIC records additional, more-detailed, flow information for the switch. The processor can then receive, from the modified ASIC, the additional flow information. The additional flow information can then be used (either by the processor or by an operator) to identify the exact reason for the errors in the flow path.

公开(公告)号：US20170212684A1

公开(公告)日：2017-07-27

申请号：US15004615

申请日：2016-01-22

Applicant: Cisco Technology, Inc.

Inventor： Sarang Dharmapurikar ,  Ganlin Wu ,  Alex Seibulescu ,  Wanli Wu

IPC: G06F3/06 ,  H04L12/26 ,  G06F12/02

CPC classification number: G06F3/0605 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0673 ,  G06F12/023 ,  G06F2212/1044 ,  G06F2212/154 ,  H04L43/08

Abstract: According to one aspect, a method includes determining whether at least one memory storage unit in a first stage of a multi-stage array is available for use by a first counter associated with the first stage, and allocating the at least one memory storage unit for use by the first counter when the at least one memory storage unit is available. When the at least one memory storage unit is not available for use by the first counter, the method includes identifying a second counter stored in a first location in the first stage, the first location including a first memory storage unit and a second memory storage unit, and moving the second counter to a second stage of the multi-stage array, storing a pointer to the second stage in the first memory storage unit, and allocating the second memory storage unit to the first counter.

公开(公告)号：US10305799B2

公开(公告)日：2019-05-28

申请号：US15239164

申请日：2016-08-17

Applicant: Cisco Technology, Inc.

Inventor： Sarang Dharmapurikar ,  Kit Chiu ,  Ganlin Wu ,  Alexandru Seibulescu ,  Francisco Matus ,  Wanli Wu

IPC: H04L12/741 ,  H04L29/06 ,  H04L12/935

Abstract: Presented herein are techniques for performing packet forwarding or routing using a pipeline of a plurality of tiles. A method includes receiving a packet, parsing the packet to generate a vector, passing the vector to a first tile dedicated to a first type of lookup, performing a lookup in the first tile, storing a result of the first type of lookup in the vector to obtain a first updated vector, passing the first updated vector to a second tile dedicated to a second type of lookup, performing a lookup in the second tile, storing a result of the second type of lookup in the vector to obtain a second updated vector, and transmitting the packet from the network routing device via an output port thereof selected based on the second updated vector.

公开(公告)号：US20180054385A1

公开(公告)日：2018-02-22

申请号：US15239164

申请日：2016-08-17

Applicant: Cisco Technology, Inc.

Inventor： Sarang Dharmapurikar ,  Kit Chiu ,  Ganlin Wu ,  Alexandru Seibulescu ,  Francisco Matus ,  Wanli Wu

IPC: H04L12/741 ,  H04L29/06 ,  H04L12/935

CPC classification number: H04L45/74 ,  H04L49/3063 ,  H04L69/22

Abstract: Presented herein are techniques for performing packet forwarding or routing using a pipeline of a plurality of tiles. A method includes receiving a packet, parsing the packet to generate a vector, passing the vector to a first tile dedicated to a first type of lookup, performing a lookup in the first tile, storing a result of the first type of lookup in the vector to obtain a first updated vector, passing the first updated vector to a second tile dedicated to a second type of lookup, performing a lookup in the second tile, storing a result of the second type of lookup in the vector to obtain a second updated vector, and transmitting the packet from the network routing device via an output port thereof selected based on the second updated vector.

公开(公告)号：US09817574B2

公开(公告)日：2017-11-14

申请号：US15004615

申请日：2016-01-22

Applicant: Cisco Technology, Inc.

Inventor： Sarang Dharmapurikar ,  Ganlin Wu ,  Alex Seibulescu ,  Wanli Wu

IPC: G06F3/06 ,  G06F12/02 ,  H04L12/26

CPC classification number: G06F3/0605 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0673 ,  G06F12/023 ,  G06F2212/1044 ,  G06F2212/154 ,  H04L43/08

Abstract: According to one aspect, a method includes determining whether at least one memory storage unit in a first stage of a multi-stage array is available for use by a first counter associated with the first stage, and allocating the at least one memory storage unit for use by the first counter when the at least one memory storage unit is available. When the at least one memory storage unit is not available for use by the first counter, the method includes identifying a second counter stored in a first location in the first stage, the first location including a first memory storage unit and a second memory storage unit, and moving the second counter to a second stage of the multi-stage array, storing a pointer to the second stage in the first memory storage unit, and allocating the second memory storage unit to the first counter.